Abstract: The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably non-identical, for example, being of different gauges and/or material composition. According to a preferred embodiment of the invention, dual capillary bond head apparatus includes a rotatable ultrasonic horn with a pair of capillaries for selectably dispensing separate strands of bond wire and for forming bonds on bond targets. According to another aspect of the invention, a method is provided for dual capillary IC wirebonding including steps for using two dual capillary bond heads for contemporaneously attaching non-identical bond wires to selected bond targets on one or more IC package assemblies.

Abstract: The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.

Abstract: The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.

Abstract: The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.

Abstract: A routing engine for use with a mounter having a chip selector and a method of routing a chip selector of a mounter. In one embodiment, the routing engine includes: (1) a memory configured to receive and store an electronic wafer map that contains coordinates and characterizations of chips of a particular wafer and (2) a travel path generator associated with the memory and configured to employ a heuristic analysis routine to generate a non-raster travel path for the chip selector to traverse with respect to the particular wafer that is shorter than a serpentine raster travel path.

Abstract: Embodiments of the present disclosure provide a routing engine, a method of routing a test probe and a testing system employing the router or the method. In one embodiment, the routing engine is for use with a test unit having at least one test probe and includes an analysis unit configured to analyze alternative test probe routing sequences that employ representative circuit chips of a semiconductor wafer to be tested by the test unit. The routing engine also includes a selection unit configured to select at least one of the test probe routing sequences as a test probe path for testing the semiconductor wafer based on a total cost of travel for the test probe path.

Abstract: The disclosure provides a semiconductor device and method of manufacture. The method for manufacturing the semiconductor device includes providing a substrate having circuitry located thereover. The surface of the substrate is subjected to a first anisotropic etch, the first anisotropic etch forming an opening that extends only partially into the substrate. An opposing surface of the substrate is subjected to a second anisotropic etch, the second anisotropic etch forming an opposing opening that extends only partially into the substrate. Additionally, a first conductive layer is formed in electrical contact with the circuitry and lining sidewalls of the opening. A second conductive layer is formed along at least a portion of the second opposing surface and lining sidewalls of the opposing opening. The first conductive layer and the second conductive layer electrically contact one another.

Abstract: Embodiments of the present disclosure provide a routing engine, a method of routing a test probe and a testing system employing the router or the method. In one embodiment, the routing engine is for use with a test unit having at least one test probe and includes an analysis unit configured to analyze alternative test probe routing sequences that employ representative circuit chips of a semiconductor wafer to be tested by the test unit. The routing engine also includes a selection unit configured to select at least one of the test probe routing sequences as a test probe path for testing the semiconductor wafer based on a total cost of travel for the test probe path.

Abstract: The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.

Abstract: A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the sample parameters are measured and if the die passes the sample parameters the die is good and repeat the steps of determining if the die is within specification and measuring the sample parameters until a die fails the measurement test or requires a trimming and if a die fails a measurement test or requires trimming perform 100 percent test and trim.

Abstract: A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.

Abstract: A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the sample parameters are measured and if the die passes the sample parameters the die is good and repeat the steps of determining if the die is within specification and measuring the sample parameters until a die fails the measurement test or requires a trimming and if a die fails a measurement test or requires trimming perform 100 percent test and trim.

Abstract: A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.

Abstract: A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.