Abstract: A method for providing reduced power consumption in a computer memory system is provided. The method includes calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, where the second operating speed is higher than the first operating speed. The method also includes operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system. The method further includes operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory. The backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system.

Abstract: A method for providing reduced power consumption in a computer memory system is provided. The method includes transferring, by a memory controller coupled to a volatile memory, a non-volatile memory, and a buffer, first data from the volatile memory to the buffer. The buffer stores less data than the volatile memory and the non-volatile memory. The method also includes placing the volatile memory into self-refresh mode after transferring the first data to the buffer. The method further includes conveying the first data from the buffer to the non-volatile memory, where the amount of first data exceeds a predetermined threshold. While conveying the first data, the memory controller takes the volatile memory out of self-refresh mode when the amount of first data in the buffer reaches the predetermined threshold. The volatile memory is ready to transfer second data to the buffer when the memory controller is finished transferring the first data.

Abstract: A method for providing reduced power consumption in a computer memory system is provided. The method includes transferring, by a memory controller coupled to a volatile memory, a non-volatile memory, and a buffer, first data from the volatile memory to the buffer. The buffer stores less data than the volatile memory and the non-volatile memory. The method also includes placing the volatile memory into self-refresh mode after transferring the first data to the buffer. The method further includes conveying the first data from the buffer to the non-volatile memory, where the amount of first data exceeds a predetermined threshold. While conveying the first data, the memory controller takes the volatile memory out of self-refresh mode when the amount of first data in the buffer reaches the predetermined threshold. The volatile memory is ready to transfer second data to the buffer when the memory controller is finished transferring the first data.

Abstract: A method for providing reduced power consumption in a computer memory system is provided. The method includes calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, where the second operating speed is higher than the first operating speed. The method also includes operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system. The method further includes operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory. The backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system.

Abstract: A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors.

Abstract: A write-caching RAID controller is disclosed. The controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to storage devices when a main power source is supplying power to the RAID controller. A memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.

Abstract: A system for performing an efficient mirrored posted-write operation having first and second RAID controllers in communication via a PCI-Express link is disclosed. The first bus bridge transmits a PCI-Express memory write request TLP to the second bus bridge. The TLP header includes an indication of whether the first CPU requests a certification that certifies the payload data has been written to the second write cache memory. If the indication requests the certification, the second bus bridge automatically transmits the certification to the first bus bridge independent of the second CPU, after writing the payload data to the second write cache memory. The first bus bridge generates an interrupt to the first CPU in response to receiving the certification. The certified transfer may be used to validate and/or invalidate mirrored copies of a write cache directory on the RAID controllers, among other uses.

Abstract: A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors.

Abstract: A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.