Abstract: A method of exploiting activation sparsity in deep neural networks is described. The method includes retrieving an activation tensor and a weight tensor where the activation tensor is a sparse activation tensor. The method also includes generating a compressed activation tensor comprising non-zero activations of the activation tensor, where the compressed activation tensor has fewer columns than the activation tensor. The method further includes processing the compressed activation tensor and the weight tensor to generate an output tensor.

Abstract: A method of exploiting activation sparsity in deep neural networks is described. The method includes retrieving an activation tensor and a weight tensor where the activation tensor is a sparse activation tensor. The method also includes generating a compressed activation tensor comprising non-zero activations of the activation tensor, where the compressed activation tensor has fewer columns than the activation tensor. The method further includes processing the compressed activation tensor and the weight tensor to generate an output tensor.

Abstract: Dynamic clock voltage scaling (DCVS) based on application performance in a system-on-a-chip (SOC), and related methods and processor-based systems are disclosed. In this regard, in one embodiment, a method of providing an application-specific DCVS in a SOC is provided. The method comprises receiving performance data corresponding to at least one performance characteristic of a SOC indicative of an execution performance of an application executing on the SOC. The method also comprises storing the performance data for the application executing on the SOC. The method further comprises, responsive to executing the application on the SOC, determining an application-specific DCVS setting for the application based on the performance data, and setting a DCVS parameter of the SOC based on the determined application-specific DCVS setting for the application. In this manner, an optimal DCVS setting is provided for the SOC to optimize computing resources, thus improving perceived performance of the application.

Abstract: The present disclosure describes methods, computer-readable media, and apparatuses for operating neural networks. For example, a first apparatus may receive a set of sparse weight vectors. The first apparatus may compress the set of sparse weight vectors to produce a compressed set of sparse weight vectors. The first apparatus may operate a neural network based on the compressed set of sparse weight vectors. In another example, a second apparatus may receive a set of sparse weight vectors. The second apparatus may perform a sparse computation based on the set of sparse weight vectors, and the performance of the sparse computation may produce one or more partial sums. The second apparatus may operate a neural network based at least in part on the one or more partial sums.

Abstract: Methods, systems and devices are provided for blocking spoiler content from being presented by a content presenting device to a user of a mobile computing device. The content presenting device and the mobile computing device may communicate using a networking framework. One or more spoiler alert events received by the content presenting device via the communication networking framework from the mobile computing device include information associated with content that has not been viewed by a user of the mobile computing device. The information associated with the content that has not been viewed is compared with the content to be presented. It may be determined whether the content to be presented by the content presenting device includes the spoiler content, and, if so, the presentation of the spoiler content by the content presenting device is restricted.

Abstract: Dynamic clock voltage scaling (DCVS) based on application performance in a system-on-a-chip (SOC), and related methods and processor-based systems are disclosed. In this regard, in one embodiment, a method of providing an application-specific DCVS in a SOC is provided. The method comprises receiving performance data corresponding to at least one performance characteristic of a SOC indicative of an execution performance of an application executing on the SOC. The method also comprises storing the performance data for the application executing on the SOC. The method further comprises, responsive to executing the application on the SOC, determining an application-specific DCVS setting for the application based on the performance data, and setting a DCVS parameter of the SOC based on the determined application-specific DCVS setting for the application. In this manner, an optimal DCVS setting is provided for the SOC to optimize computing resources, thus improving perceived performance of the application.

Abstract: Methods and structure for reprogramming firmware in a storage controller using a virtual machine management (VMM) environment. A storage process (current firmware) in the storage controller operates in a current virtual machine (VM) under control of a hypervisor. Reprogrammed (new) firmware is loaded into a new virtual machine under control of the hypervisor. The new firmware initializes and directs the current firmware to quiesce its processing. The new firmware also requests the hypervisor to map data in the memory space of the current virtual machine into the memory space of the new virtual machine and to transfer ownership/control of devices and network addresses from the current virtual machine to the new virtual machine. The new firmware operating on the new virtual machine then takes control of the storage controller and resumes processing of requests.

Abstract: Methods and structure for reprogramming firmware in a storage controller using a virtual machine management (VMM) environment. A storage process (current firmware) in the storage controller operates in a current virtual machine (VM) under control of a hypervisor. Reprogrammed (new) firmware is loaded into a new virtual machine under control of the hypervisor. The new firmware initializes and directs the current firmware to quiesce its processing. The new firmware also requests the hypervisor to map data in the memory space of the current virtual machine into the memory space of the new virtual machine and to transfer ownership/control of devices and network addresses from the current virtual machine to the new virtual machine. The new firmware operating on the new virtual machine then takes control of the storage controller and resumes processing of requests.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a viral entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame"s destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.