Abstract: A combination for electrically connecting an integrated circuit (14) to a lead frame package (18) comprises a first jumper chip (16) and a plurality of bonding wires (20) including at least a first bonding wire and a second bonding wire. The first bonding wire extends between and electrically connects the first jumper chip (16) and the lead frame package (18). Additionally, the second bonding wire extends between and electrically connects the first jumper chip (16) and the integrated circuit (14). The plurality of bonding wires (20) can further include a third bonding wire that extends between and electrically connects the integrated circuit (14) and the lead frame package (18). Further, the combination can also comprise a second jumper chip (216B), and the plurality of bonding wires (20) can further include a third bonding wire and a fourth bonding wire. The third bonding wire can extend between and electrically connect the second jumper chip (216B) and the lead frame package (18).

Abstract: A test structure for an integrated circuit having a first underlying conductive layer. A first nonconductive layer is disposed over the first underlying conductive layer, and a first overlying conductive layer is disposed over the first nonconductive layer. First conductive vias form electrical connections between the first underlying conductive layer and the first overlying conductive layer. A second overlying conductive layer is disposed over the first nonconductive layer, but the second overlying conductive layer does not make electrical connections to the first underlying conductive layer. The test structure also has a second underlying conductive layer. A second nonconductive layer is disposed over the second underlying conductive layer, with a third overlying conductive layer disposed over the second nonconductive layer. The third overlying conductive layer does not make electrical connections to the second underlying conductive layer.

Abstract: A test structure for an integrated circuit having a first underlying conductive layer. A first nonconductive layer is disposed over the first underlying conductive layer, and a first overlying conductive layer is disposed over the first nonconductive layer. First conductive vias form electrical connections between the first underlying conductive layer and the first overlying conductive layer. A second overlying conductive layer is disposed over the first nonconductive layer, but the second overlying conductive layer does not make electrical connections to the first underlying conductive layer. The test structure also has a second underlying conductive layer. A second nonconductive layer is disposed over the second underlying conductive layer, with a third overlying conductive layer disposed over the second nonconductive layer. The third overlying conductive layer does not make electrical connections to the second underlying conductive layer.

Abstract: A method of forming a low loop height wire interconnection in a semiconductor package including a die having a multiple row bond pad layout, and a wire bonded electrical interconnection formed using the method consists of the steps: forming a first ball bond from a first wire at a first bonding location; looping the first wire to a first bond pad of a die; forming a first stitch bond between the first wire and the first bond pad; forming a second ball bond from a second wire at a second bond pad of the die; looping the second wire to a second bonding location, wherein the second wire does not contact the first wire; and forming a second stitch bond between the second wire and the second bonding location.