Patents by Inventor Reynaldo V. Villavelez

Reynaldo V. Villavelez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190248157
    Abstract: In some examples, a heater assembly for a pattern forming system includes a support, and heating elements mounted on the support, where the heating elements are to, in response to activation of the heating element, produce heat directed towards a target to form a pattern on the target. A heat sink is thermally connected to the heating elements and comprising a pattern of heat dissipation surfaces comprising channels to dissipate heat produced by the heating elements.
    Type: Application
    Filed: October 20, 2016
    Publication date: August 15, 2019
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Reynaldo V Villavelez, Terry McMahon, Donald W Schulte
  • Patent number: 10319728
    Abstract: In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 11, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chaw Sing Ho, Reynaldo V. Villavelez, Xin Ping Cao
  • Publication number: 20180006045
    Abstract: The present subject matter relates to an electrical programmable read only memory (EPROM) cell. The EPROM cell comprises a semiconductor substrate and a floating gate separated from the semiconductor substrate by a first dielectric layer. A control gate is capacitively coupled to the floating gate through a second dielectric layer disposed between the floating gate and the control gate. In an example, the EPROM cell further comprises a conductive gate connected to the floating gate, wherein the conductive gate is to leak charges from the floating gate in a predetermined leak time period.
    Type: Application
    Filed: January 29, 2015
    Publication date: January 4, 2018
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Boon Bing Ng, Lui Cheat Thin, Reynaldo V Villavelez
  • Patent number: 9776397
    Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a bank of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the cells. A shift register circuit is coupled to at least one of the row select port and the column select port of each of the cells, the shift register circuit storing samples of an input signal responsive to a plurality of clock signals. A decoder is coupled to the shift register circuit to provide the input signal based on a logical combination of a plurality of data signals and at least a portion of the clock signals.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: October 3, 2017
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Reynaldo V Villavelez
  • Publication number: 20170106648
    Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a bank of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the cells. A shift register circuit is coupled to at least one of the row select port and the column select port of each of the cells, the shift register circuit storing samples of an input signal responsive to a plurality of clock signals. A decoder is coupled to the shift register circuit to provide the input signal based on a logical combination of a plurality of data signals and at least a portion of the clock signals.
    Type: Application
    Filed: April 17, 2014
    Publication date: April 20, 2017
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning GE, Reynaldo V Villavelez
  • Publication number: 20170092653
    Abstract: In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.
    Type: Application
    Filed: December 14, 2016
    Publication date: March 30, 2017
    Inventors: Chaw Sing Ho, Reynaldo V. Villavelez, Xin Ping Cao
  • Publication number: 20170062449
    Abstract: A memory cell for a printhead includes a substrate with a source and a drain. The substrate further includes a channel located between the source and the drain and surrounding the drain. The drain can include a first rounded closed curved structure. The memory cell can include a floating gate and a control gate. The floating gate can include a second rounded closed curve structure located above the channel and below the control gate. The control gate is capacitively coupled to the floating gate.
    Type: Application
    Filed: November 15, 2016
    Publication date: March 2, 2017
    Inventors: Reynaldo V. Villavelez, Paul I. Mikulan
  • Publication number: 20170053993
    Abstract: The present subject matter relates to an integrated circuit. The integrated circuit includes a first metal layer and a second metal layer capacitively coupled to the first metal layer through a dielectric layer. Further, the second metal layer includes an electron leakage path to provide for leakage of charge from the second metal layer in a predetermined leak time period.
    Type: Application
    Filed: April 30, 2014
    Publication date: February 23, 2017
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Reynaldo V Villavelez, Ning GE, Mun Hooi YAOW, Erik D Ness, David B Novak
  • Patent number: 9524780
    Abstract: A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: December 20, 2016
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Reynaldo V Villavelez, Paul I. Mikulan
  • Publication number: 20130329498
    Abstract: A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.
    Type: Application
    Filed: March 15, 2011
    Publication date: December 12, 2013
    Inventors: Reynaldo V. Villavelez, Paul I. Mikulan
  • Patent number: 8444255
    Abstract: A thermal inkjet printhead may include a substrate and a resistive layer. A thermal resistor may be formed in the resistive layer. A first metal layer may be between the substrate and a resistive layer having a thickness to form a power bus. A dielectric layer may be between the first metal layer and the resistive layer.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: May 21, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chris Bakker, Lawrence H. White, Bjorn Warloe, Reynaldo V. Villavelez, Paul I. Mikulan, Kenneth Stewart, Michael Allen Godwin, Teck-Khim Neo, Joseph M. Torgerson, Lonnie Byers
  • Publication number: 20120293587
    Abstract: A thermal inkjet printhead may include a substrate and a resistive layer. A thermal resistor may be formed in the resistive layer. A first metal layer may be between the substrate and a resistive layer having a thickness to form a power bus. A dielectric layer may be between the first metal layer and the resistive layer.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 22, 2012
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chris Bakker, Lawrence H. White, Bjorn Warloe, Reynaldo V. Villavelez, Paul I. Mikulan, Kenneth Stewart, Michael Allen Godwin, Teck-Khim Neo, Joe Torgerson, Lonnie Byers