Patents by Inventor Reynante T. Alvarado

Reynante T. Alvarado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer-level packaged device having self-assembled resilient leads
    Patent number: 8692367
    Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: April 8, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Chiung C. Lo, Arkadii V. Samoilov, Reynante T. Alvarado
  • WAFER-LEVEL PACKAGED DEVICE HAVING SELF-ASSEMBLED RESILIENT LEADS
    Publication number: 20110198745
    Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.
    Type: Application
    Filed: February 17, 2010
    Publication date: August 18, 2011
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Chiung C. Lo, Arkadii V. Samoilov, Reynante T. Alvarado
  • Deformation-absorbing leadframe for semiconductor devices
    Publication number: 20020190358
    Abstract: A leadframe structure for use with an integrated circuit chip, comprising a chip mount pad having an area smaller than said chip intended for mounting; a plurality of support members, each attached externally to the perimeter of said pad and internally to said leadframe; and each said support member having at least one portion located within the perimeter of said chip in a configuration operable to absorb thermally induced deformations of said support member.
    Type: Application
    Filed: August 6, 2002
    Publication date: December 19, 2002
    Inventors: Ronaldo M. Arguelles, Reynante T. Alvarado, Leonardo S. Rimpillo, Teddy D. Weygan
  • Deformation-absorbing leadframe for semiconductor devices
    Patent number: 6455922
    Abstract: A leadframe structure for use with an integrated circuit chip, comprising a chip mount pad having an area smaller than said chip intended for mounting; a plurality of support members, each attached externally to the perimeter of said pad and internally to said leadframe; and each said support member having at least one portion located within the perimeter of said chip in a configuration operable to absorb thermally induced deformations of said support member.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: September 24, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Ronaldo M. Arguelles, Reynante T. Alvarado, Leonardo S. Rimpillo, Jr., Teddy D. Weygan