Patents by Inventor Reza Arghavani

Reza Arghavani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6809017
    Abstract: Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: October 26, 2004
    Assignee: Intel Corporation
    Inventors: Reza Arghavani, Robert Chau, Mark Doczy, Brian Roberds
  • Publication number: 20040161903
    Abstract: A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes depositing a first portion of a film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing processing gas and the oxidizing gas. Depositing the conformal layer includes varying over time a ratio of the (silicon-containing processing gas):(oxidizing gas) and regulating the chamber to a pressure in a range from about 200 torr to about 760 torr throughout deposition of the conformal layer. The method also includes depositing a second portion of the film as a bulk layer.
    Type: Application
    Filed: January 14, 2004
    Publication date: August 19, 2004
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Zheng Yuan, Reza Arghavani, Shankar Venkataraman
  • Publication number: 20040118805
    Abstract: A method for anisotropically and selectively removing a dielectric thin film layer from a substrate layer is disclosed, wherein the dielectric layer is subjected to ion implantation prior to wet etching. This method may be applied adjacent to a structure such as a gate electrode within a microelectronic structure to prevent undercutting of the dielectric material to be preserved between the gate electrode and the substrate layer, as may happen with more isotropic etching techniques.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Inventors: Scott A. Hareland, Nick Lindert, Reza Arghavani, Robert Chau
  • Publication number: 20040106287
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.
    Type: Application
    Filed: July 11, 2003
    Publication date: June 3, 2004
    Inventors: Robert Chau, Reza Arghavani, Mark Doczy
  • Patent number: 6713358
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate. After forming a silicon nitride layer on the high-k gate dielectric layer, a gate electrode is formed on the silicon nitride layer.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: March 30, 2004
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Timothy E. Glassman, Christopher G. Parker, Matthew V. Metz, Lawrence J. Foley, Reza Arghavani, Douglas W. Barlage
  • Patent number: 6707120
    Abstract: A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: March 16, 2004
    Assignee: Intel Corporation
    Inventors: Payman Aminzadeh, Reza Arghavani, Peter Moon
  • Publication number: 20040036123
    Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.
    Type: Application
    Filed: August 26, 2003
    Publication date: February 26, 2004
    Inventors: Steven J. Keating, Robert S. Chau, Reza Arghavani, Jack T. Kavalieros, Douglas W. Barlage
  • Publication number: 20040033677
    Abstract: A method and apparatus of preventing lateral oxidation through gate dielectrics that are highly permeable to oxygen diffusion, such as high-k gate dielectrics. According to one embodiment of the invention, a gate structure is formed on a substrate, the gate structure having an oxygen-permeable gate dielectric. An oxygen diffusion barrier is then formed on the sidewalls of the gate structure to prevent oxygen from diffusing laterally into the oxygen-permeable gate dielectric, thus preventing oxidation to the substrate underneath the gate dielectric or to the electrically conductive gate electrode overlying the gate dielectric.
    Type: Application
    Filed: August 14, 2002
    Publication date: February 19, 2004
    Inventors: Reza Arghavani, Patricia Stokley, Robert Chau
  • Publication number: 20040031990
    Abstract: A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers.
    Type: Application
    Filed: August 16, 2002
    Publication date: February 19, 2004
    Inventors: Been-Yih Jin, Reza Arghavani, Robert Chau
  • Publication number: 20040033678
    Abstract: A method and apparatus of preventing lateral oxidation through gate dielectrics that are highly permeable to oxygen diffusion, such as high-k gate dielectrics. According to one embodiment of the invention, a gate structure is formed on a substrate, the gate structure having an oxygen-permeable gate dielectric. An oxygen diffusion barrier is then formed on the sidewalls of the gate structure to prevent oxygen from diffusing laterally into the oxygen-permeable gate dielectric, thus preventing oxidation to the substrate underneath the gate dielectric or to the electrically conductive gate electrode overlying the gate dielectric.
    Type: Application
    Filed: March 25, 2003
    Publication date: February 19, 2004
    Inventors: Reza Arghavani, Patricia Stokley, Robert Chau
  • Patent number: 6667232
    Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Steven J. Keating, Robert S. Chau, Reza Arghavani, Jack T. Kavalieros, Douglas W. Barlage
  • Patent number: 6667251
    Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes nitridizing a thin silicon oxide film in a low power, direct plasma formed from nitrogen. A gas having a lower ionization energy than nitrogen, such as for example, helium, may be used in combination with nitrogen to produce a lower power plasma resulting in a steeper concentration curve for nitrogen in the silicon oxide film.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Robert McFadden, Jack Kavalieros, Reza Arghavani, Doug Barlage, Robert Chau
  • Publication number: 20030216059
    Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes nitridizing a thin silicon oxide film in a low power, direct plasma formed from nitrogen. A gas having a lower ionization energy than nitrogen, such as for example, helium, may be used in combination with nitrogen to produce a lower power plasma resulting in a steeper concentration curve for nitrogen in the silicon oxide film.
    Type: Application
    Filed: June 11, 2003
    Publication date: November 20, 2003
    Inventors: Robert McFadden, Jack Kavalieros, Reza Arghavani, Doug Barlage, Robert Chau
  • Patent number: 6620713
    Abstract: Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: September 16, 2003
    Assignee: Intel Corporation
    Inventors: Reza Arghavani, Robert Chau, Mark Doczy, Brian Roberds
  • Patent number: 6617209
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: September 9, 2003
    Assignee: Intel Corporation
    Inventors: Robert Chau, Reza Arghavani, Mark Doczy
  • Patent number: 6617210
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. An insulating layer, which is compatible with the dielectric layer and a gate electrode to be formed on the insulating layer, is formed on the dielectric layer, and a gate electrode is then formed on the insulating layer.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: September 9, 2003
    Assignee: Intel Corporation
    Inventors: Robert Chau, Reza Arghavani
  • Publication number: 20030162377
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.
    Type: Application
    Filed: February 22, 2002
    Publication date: August 28, 2003
    Inventors: Robert Chau, Reza Arghavani, Mark Doczy
  • Patent number: 6610615
    Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes nitridizing a thin silicon oxide film in a low power, direct plasma formed from nitrogen. A gas having a lower ionization energy than nitrogen, such as for example, helium, may be used in combination with nitrogen to produce a lower power plasma resulting in a steeper concentration curve for nitrogen in the silicon oxide film.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: August 26, 2003
    Assignee: Intel Corporation
    Inventors: Robert McFadden, Jack Kavalieros, Reza Arghavani, Doug Barlage, Robert Chau
  • Patent number: 6597046
    Abstract: An integrated circuit includes insulated gate field effect transistors (IGFETs), having gate dielectric layers wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and a second concentration at the gate dielectric/substrate interface. In one embodiment the gate dielectric is an oxynitride formed by an N2 plasma; and the oxynitride has top surface nitrogen concentration that is higher than a bottom surface nitrogen concentration. In a further aspect of the present invention, an integrated circuit includes a plurality of IGFETs, wherein various ones of the plurality of IGFETs have different gate dielectric thicknesses and compositions.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: July 22, 2003
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Reza Arghavani, Bruce Beattie
  • Publication number: 20030124871
    Abstract: Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventors: Reza Arghavani, Robert Chau, Mark Doczy, Brian Roberds