Patents by Inventor Reza Asayeh

Reza Asayeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High density antifuse based partitioned FPGA architecture
    Patent number: 6794897
    Abstract: An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. With repeatable blocks the size of the FPGA may be made larger with minimal changes to the architecture. Disposed along the edges of each repeatable block are bidirectional buffer banks for connecting to adjacent blocks and to an interconnect matrix that is connectable to blocks other than adjacent blocks. Disposed at regular intervals in the interconnect matrix are repeater buffers to limit the number of antifuses on a given track of the interconnect matrix, to minimize RC delay, and to avoid violating the Ipeak limit.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: September 21, 2004
    Assignee: Actel Corporation
    Inventor: Reza Asayeh
  • High density antifuse based partitioned FPGA architecture
    Publication number: 20030201792
    Abstract: An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. With repeatable blocks the size of the FPGA may be made larger with minimal changes to the architecture. Disposed along the edges of each repeatable block are bidirectional buffer banks for connecting to adjacent blocks and to an interconnect matrix that is connectable to blocks other than adjacent blocks. Disposed at regular intervals in the interconnect matrix are repeater buffers to limit the number of antifuses on a given track of the interconnect matrix, to minimize RC delay, and to avoid violating the Ipeak limit.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 30, 2003
    Applicant: Actel Corporation, a California Corporation
    Inventor: Reza Asayeh
  • High density antifuse based partitioned FPGA architecture
    Patent number: 6549035
    Abstract: An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. With repeatable blocks the size of the FPGA may be made larger with minimal changes to the architecture. Disposed along the edges of each repeatable block are bidirectional buffer banks for connecting to adjacent blocks and to an interconnect matrix that is connectable to blocks other than adjacent blocks. Disposed at regular intervals in the interconnect matrix are repeater buffers to limit the number of antifuses on a given track of the interconnect matrix, to minimize RC delay, and to avoid violating the Ipeak limit.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: April 15, 2003
    Assignee: Actel Corporation
    Inventor: Reza Asayeh