Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

Abstract: An embodiment of the invention is directed to a method for accessing configuration registers. An indication that an attempt has been made to access a first register is received. This first register reflects an index variable that points to a configuration register. Next, an indication that an attempt has been made to access a second register is received. This second register reflects part of the contents of a configuration register to which the index variable points. Next, without waiting for another attempt to access the first register, the index variable is changed to point to another configuration register. Other embodiments are also described and claimed.

Abstract: In an integrated circuit socket an integrating capacitor filter carried on a mylar film or integral with said socket incorporated into the top of an integrated circuit socket electrically connected to the voltage and ground connecting pins or electrodes of the integrated circuit in as close as proximity to the entry point into the integrated circuit as is possible. This reduces the lead distance between the entry point in the integrated circuit including CPU integrated circuits at both the voltage and ground connection and the capacitive element to a minimum and minimizes interference in the power source by minimizing inductance in capacitor leads experienced in high speed electrical circuits. It is particular useful in minimizing electrical interference in the voltage applied to CPU by incorporating the capacitive element directly into the CPU socket so that it is electrically coupled between the voltage pin and the ground pin of the CPU in close proximity to the entry point in the CPU.

Abstract: A computer system includes a chipset which controls the gate-A20 signal and the CPU RESET signal in a conventional manner in response to commands from a system microprocessor. The computer system further includes a peripheral controller which is programmed to generate an alternative gate-A20 signal and an alternative CPU RESET signal when the peripheral controller has been commanded to override the corresponding signals from the chipset. Two signal selectors controlled by the peripheral controller select either the gate-A20 signal and the CPU RESET signal from the chipset or the alternative gate-A20 signal and the alternative CPU RESET signal from the peripheral controller as respective outputs to control operations of the computer system. The use of the alternative signals permits certain operations of the computer systems to be directly controlled by an application program without being intercepted by the operating system.