Patents by Inventor Reza Jalilizeinali
Reza Jalilizeinali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411956Abstract: Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.Type: ApplicationFiled: August 2, 2023Publication date: December 21, 2023Inventors: Sreeker DUNDIGAL, Reza JALILIZEINALI, Krishna Chaitanya CHILLARA, Wen-Yi CHEN
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Patent number: 11575259Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad.Type: GrantFiled: July 8, 2021Date of Patent: February 7, 2023Assignee: QUALCOMM INCORPORATEDInventors: Wen-Yi Chen, Reza Jalilizeinali, Sreeker Dundigal, Krishna Chaitanya Chillara, Gregory Lynch
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Publication number: 20230008489Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Inventors: Wen-Yi CHEN, Reza JALILIZEINALI, Sreeker DUNDIGAL, Krishna Chaitanya CHILLARA, Gregory LYNCH
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Publication number: 20210407990Abstract: A chip includes a pad and a driver having an output coupled to the pad. The chip also includes one or more diodes coupled between the pad and a ground bus, wherein the one or more diodes are in a forward direction from the pad to the ground bus.Type: ApplicationFiled: June 22, 2021Publication date: December 30, 2021Inventors: Sreeker DUNDIGAL, Reza JALILIZEINALI, Krishna Chaitanya CHILLARA, Wen-Yi CHEN
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Publication number: 20210408786Abstract: Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.Type: ApplicationFiled: June 22, 2021Publication date: December 30, 2021Inventors: Sreeker DUNDIGAL, Reza JALILIZEINALI, Krishna Chaitanya CHILLARA, Wen-Yi CHEN
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Patent number: 11171649Abstract: An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.Type: GrantFiled: October 15, 2020Date of Patent: November 9, 2021Assignee: QUALCOMM INCORPORATEDInventors: Aliasgar Presswala, Wilson Jianbo Chen, Chiew-Guan Tan, Reza Jalilizeinali
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Patent number: 10298010Abstract: A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.Type: GrantFiled: March 31, 2016Date of Patent: May 21, 2019Assignee: QUALCOMM IncorporatedInventors: Eugene Robert Worley, Reza Jalilizeinali, Sreeker Dundigal, Wen-Yi Chen, Krishna Chaitanya Chillara, Taeghyun Kang
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Patent number: 10114074Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.Type: GrantFiled: April 17, 2018Date of Patent: October 30, 2018Assignee: QUALCOMM IncorporatedInventors: Alvin Leng Sun Loke, Thomas Clark Bryan, Reza Jalilizeinali, Tin Tin Wee, Stephen Robert Knol, Luverne Ray Peterson
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Publication number: 20180231608Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.Type: ApplicationFiled: April 17, 2018Publication date: August 16, 2018Inventors: Alvin Leng Sun Loke, Thomas Clark Bryan, Reza Jalilizeinali, Tin Tin Wee, Stephen Robert Knol, Luverne Ray Peterson
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Patent number: 9977078Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.Type: GrantFiled: July 23, 2014Date of Patent: May 22, 2018Assignee: QUALCOMM IncorporatedInventors: Alvin Leng Sun Loke, Thomas Clark Bryan, Reza Jalilizeinali, Tin Tin Wee, Stephen Robert Knol, LuVerne Ray Peterson
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Patent number: 9800230Abstract: A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX>CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.Type: GrantFiled: June 29, 2016Date of Patent: October 24, 2017Assignee: QUALCOMM IncorporatedInventors: Wilson Chen, Chiew-Guan Tan, Reza Jalilizeinali
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Publication number: 20170288398Abstract: A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Eugene Robert WORLEY, Reza JALILIZEINALI, Sreeker DUNDIGAL, Wen-Yi CHEN, Krishna Chaitanya CHILLARA, Taeghyun KANG
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Patent number: 9762231Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.Type: GrantFiled: July 29, 2015Date of Patent: September 12, 2017Assignee: QUALCOMM IncorporatedInventors: Alvin Leng Sun Loke, Bo Yu, Stephen Clifford Thilenius, Reza Jalilizeinali, Patrick Isakanian
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Patent number: 9614529Abstract: An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (VPAD) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while VPAD continues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when VPAD begins transitioning from high to low logic voltages, and transitions back to the low bias voltage while VPAD continues to transition towards the low logic voltage.Type: GrantFiled: February 1, 2016Date of Patent: April 4, 2017Assignee: QUALCOMM IncorporatedInventors: Wilson Chen, Chiew-Guan Tan, Reza Jalilizeinali
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Patent number: 9484911Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.Type: GrantFiled: February 25, 2015Date of Patent: November 1, 2016Assignee: QUALCOMM IncorporatedInventors: Wilson Jianbo Chen, Chiew-Guan Tan, Reza Jalilizeinali
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Publication number: 20160269017Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.Type: ApplicationFiled: July 29, 2015Publication date: September 15, 2016Inventors: Alvin Leng Sun Loke, Bo Yu, Stephen Clifford Thilenius, Reza Jalilizeinali, Patrick Isakanian
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Publication number: 20160248418Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.Type: ApplicationFiled: February 25, 2015Publication date: August 25, 2016Inventors: Wilson Jianbo Chen, Chiew-Guan Tan, Reza Jalilizeinali
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Patent number: 9406627Abstract: A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant.Type: GrantFiled: September 26, 2013Date of Patent: August 2, 2016Assignee: QUALCOMM INCORPORATEDInventors: Eugene Robert Worley, Reza Jalilizeinali, Sreeker Dundigal
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Patent number: 9368648Abstract: An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed.Type: GrantFiled: March 31, 2010Date of Patent: June 14, 2016Assignee: QUALCOMM IncorporatedInventors: Reza Jalilizeinali, Eugene R. Worley, Evan Siansuri, Sreeker R. Dundigal
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Publication number: 20160025807Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.Type: ApplicationFiled: July 23, 2014Publication date: January 28, 2016Inventors: Alvin Leng Sun Loke, Thomas Clark Bryan, Reza Jalilizeinali, Tin Tin Wee, Stephen Robert Knol, LuVerne Ray Peterson