Abstract: A row decoder for controlling a plurality of selectable word-lines has one control line per block of N word-lines, K select lines, at least one disable line and one word-line driver per word-line. Each control line is activatable during a charge period and during an initial portion of a discharge period. Each select line is selectably high during the charge period. The disable line is active during the discharge period. Each driver includes an access transistor and a discharge transistor. The access transistor is located at one end of its word-line and the discharge transistor is connected at the other end. The access transistor is controlled by one control line and is connected between one select line and the word-line. The discharge transistor is controlled by one disable signal and is connected between the word-line and a ground supply.

Abstract: A dual bit memory cell includes a substrate, a gate unit and left and right diffusions implanted into the substrate on the outer sides of the gate unit such that a channel exists under the gate unit and between the left and right diffusions. The gate unit includes a control gate and left and right separately programmable floating gates located on the left and right sides of the control gate. Each floating gate controls a short portion of the channel. The left diffusion acts as a drain and the right diffusion acts as a source when reading the value stored in the right floating gate and the right diffusion acts as a drain and the left diffusion as a source when reading the value stored in the left floating gate. In one embodiment, the floating gates are formed of polysilicon spacers.

Abstract: An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.

Abstract: The leakage current through a static random access memory ("SRAM") containing a plurality of memory cells connected between a voltage supply and a reference voltage, wherein each memory cell uses native transistors as load elements, is controlled by controlling the reference voltage.

Abstract: A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.

Abstract: An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.

Abstract: A unit for stabilizing the voltage on a capacitive node of a memory array, such as a common node bit line (CNBL), is disclosed. The unit includes an amplifier connected to the CNBL line and to one voltage source and a leaker connected to the CNBL line and to the other voltage supply, where the two voltage supplies can be the positive and ground supplies. The leaker is much smaller then the amplifier thereby to remove current from the CNBL line when there is little or no activity in The memory array. An alternative version of the unit which is also operative for standby operation is disclosed. In this embodiment, there is a switchable high power unit activatable during an active mode and a low power unit. Both units include an amplifier and a leaker connected as in the previous embodiment. The leakers are much smaller then the amplifiers and the amplifier of the high power unit is much larger than the amplifier of the low power unit.

Abstract: Flash EEPROM array and EPROM arrays are described. The EEPROM array has EEPROM areas with arrays of EEPROM transistors, at least one control area per EEPROM area and columns of a first polysilicon layer traversing the EEPROM and control areas. The columns are divided into even and odd columns. Each control area is divided into upper, middle and lower areas and each control area includes the following: a) within the middle area, cross-lines of the first polysilicon extending from each even to the next odd column; b) four rows of a second polysilicon layer, laid down after the columns and cross-lines of the first polysilicon layer within the control areas are removed; and c) isolating oxide elements laid down prior to the first polysilicon layer and self-aligned to it before it is removed.

Abstract: An EPROM array comprises a plurality of floating gate memory cell transistors and a multiplicity of floating gate select transistors arranged so that at least one select transistor controls the current to a group of floating gate memory cell transistors. Each floating gate select transistor remains unprogrammed or substantially unprogrammed even though the floating gate memory cell transistors in the memory array are selectively programmed to store information. The use of floating gate transistors for both memory cell transistors and select transistors simplifies the manufacturing process and improves yield.

Abstract: An electrically programmable read only memory contains alternating metal bit lines and diffused bit lines. Each diffused bit line is broken into a plurality of segments. Each of the segments of the diffused bit line comprises a virtual source. A multiplicity of floating gate transistors are arranged in rows and columns. The floating gate transistors in each column are divided into M groups of N floating gate transistors each. The floating gate transistors in the n.sup.th and the (n+1).sup.th columns, where n is an odd integer given by 1.ltoreq.n.ltoreq.N and (N+1) is the maximum number of columns in the array are connected to the segments of one diffused bit line placed between the n.sup.th and the (n+1).sup.th columns. At least one first transfer transistor is arranged to connect one segment comprising a virtual source to a first metal bit line. The first metal bit line functions as the source for the N floating gate transistors in the (n+1).sup.th column connected to said one segment.

Abstract: A method of programming a floating gate transistor permits the use of a charge pump to provide drain programming current. The programming drain current is typically held below about 1 .mu.A. This programming drain current can be provided by a conventional charge pump. In the first embodiment, the drain current can be limited by connecting a resistor between the source and ground. In a second embodiment, the drain current is limited by limiting the transistor control gate voltage. In a third embodiment, a charge pump is coupled to the drain while the control gate is repetitively pulsed. Each time the control gate is pulsed, the transistor turns on, and although the drain is initially discharged through the transistor, some hot electrons are accelerated onto the floating gate, and eventually the floating gate is programmed. In these embodiments the erase gate voltage may be raised to enhance programming efficiency.

Abstract: An EPROM array has plural rows of split gate transistors, where each transistor includes a floating gate and the floating gate has corner portions. A bit-line defining edge is formed on each floating gate between two of the corners. The bit-line defining edges of first and second floating gates respectively belonging to first and second rows are patterned so that these edges protrude into opposed side areas of a bit line implant window. This arrangement minimizes resistance changes in the bit lines due to mask misalignment. The misalignment insensitivity permits relaxation of dimensional constraints. Cells of the memory array can be drawn to have smaller areas.

Abstract: An EEPROM constructed in accordance with our invention includes a voltage multiplier for generating an erase voltage and a voltage regulator circuit for controlling the magnitude of the erase voltage. The voltage regulator circuit includes a capacitive voltage divider for providing a first voltage proportional to the erase voltage, a reference voltage lead for providing a reference voltage and a control circuit for controlling the voltage multipler circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier includes novel capacitors and transistors constructed using standard EEPROM processing to withstand high voltages without breaking down.

Abstract: An EEPROM constructed in accordance with our invention includes a voltage multiplier for generating an erase voltage and a voltage regulator circuit for controlling the magnitude of the erase voltage. The voltage regulator circuit includes means for providing a first voltage proportional to the erase voltage, means for providing a reference voltage on a reference voltage lead, and means for controlling the voltage multiplier circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier includes novel capacitors and transistors constructed using standard EEPROM processing to withstand high voltages without breaking down.

Abstract: A field effect transistor includes a source region, a drain region, and a channel region formed in a semiconductor substrate and a floating gate and a control gate formed over the substrate. An opaque cover (typically aluminum) is formed over but electrically insulated from the transistor to prevent light from striking and affecting the electrical charge on the floating gate. The periphery of the opaque cover ohmically contacts the semiconductor substrate, thereby limiting the amount of light reaching the floating gate, except where the source and drain extend inwardly beyond the periphery of the opaque cover. The control gate extends over a portion of the substrate surrounding the transistor, and helps hinder light from reaching the floating gate. In addition, semiconductor material formed concurrently with the control gate extends over the source and drain regions, thereby providing additional shading.