Abstract: A self-calibrating high speed D/A converter is provided with a calibration circuit for providing a fixed calibration current and a fixed calibration voltage during calibration mode, and a biasing circuit for biasing the calibration circuit with a first reference voltage and biasing the MSB and LSB array cells with a second reference voltage. By keeping the biasing voltage constant at the array cells during both calibrating and operating modes, such as 12 bits, the D/A converter effectively operates at high resolution, and at high operating speed.

Abstract: A demodulator circuit receives an input signal read from a track of a magnetic medium and generates a control signal to maintain alignment of a read-write head with the track. The demodulator circuit includes at least one transistor. The at least one transistor has an electrode switchable between first and second voltage sources. The electrode is coupled to the second voltage source to block processing of the input signal. The electrode is coupled to the first voltage source to process the input signal. The at least one transistor provides an effective resistance when coupled to the first voltage source that is dependent on the voltage level of the first voltage source. The at least one transistor half-wave rectifies the input signal when the electrode is coupled to the first voltage source.

Abstract: Control voltages are generated so that each transistor in a plurality of parallel connected field effect transistors turns ON with smooth transitions between transistors and in a manner that is relatively insensitive to processing and operating temperature variations.

Abstract: A method and apparatus for improving the performance of a phase-locked loop are disclosed. A phase error between two signals is sensed and a temporary increase in the bandwidth of the phase-locked loop is provided responsive to the sensed phase error. The phase-locked loop may comprise a charge pump and the temporary increase in the bandwidth of the phase-locked loop may comprise a temporary increase in charge pump current. An increase in phase-locked loop bandwidth is followed by a decrease in the bandwidth responsive to a decrease in phase error. The decrease in bandwidth may comprise a decrease in charge pump current.