Abstract: An apparatus includes a first converter circuit with a first output terminal and a second output terminal. The apparatus includes a second converter circuit with a first input terminal and a second input terminal and a third output terminal. A first connection connects the first output terminal to the first input terminal. A second connection connects the second output terminal to the second input terminal. The apparatus also includes a direct current (DC) decoupling component that is connected between the first connection and the second connection. The DC decoupling component DC decouples a signal between the first connection and the second connection.

Abstract: Methods and systems for selecting a treatment for a patient. The system extracts an incidental finding from a record associated with a patient and an associated follow-up recommendation. The system then determines whether any inconsistencies exist between the follow-up recommendation from the report and a follow-up recommendation prescribed by institutional or administrative guidelines. Any inconsistencies may then be resolved to guarantee an appropriate workflow for patient care.

Abstract: Current regulation circuits and techniques. In one example, a circuit includes a voltage regulator circuit, current sensing circuitry, and a current control loop. The voltage regulator circuit is coupled to an output terminal of a DC-DC power converter and configured to produce a regulation signal based on a voltage at a regulator input terminal. The current sensing circuitry is coupled to a switching terminal of the DC-DC power converter and configured to produce a pulse signal based on a voltage at the switching input terminal and a threshold set by the regulation signal. The current control loop is coupled to control terminals of switching transistors of the DC-DC power converter and configured to generate switching control signals, based on the pulse signal, to control the switching transistors to drive an average value of a current flowing through the switching terminal to a target average current value corresponding to the threshold.

Abstract: Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.

Abstract: Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.

Abstract: An integrated circuit (IC) package includes a one or more die and an interposer. The interposer is coupled to the die and includes circuit traces. The circuit traces are provided in a serpentine configuration. A method can be used to fabricate an integrated circuit package.

Abstract: A power converter includes a power stage circuit having a control input and an output. A pulse width modulation (PWM) controller has a control output coupled to the control input of the power stage. A compensator includes a passive component and a switch coupled to the passive component. The switch has a switch control input coupled to the control output of the PWM controller.

Abstract: The present invention is directed to semiconductor devices and integrated circuit packaging. In a specific embodiment, a semiconductor device with a heat spreader structure is provided. The heat spreader is configured to couple to a second layer to establish an effective thermal dissipation path for heat generated from a hot spot of a circuit. The second layer comprises a first portion and a second portion. The first portion is coupled to the hot spot. The heat spreader comprises a third portion and a fourth portion. The third portion comprises a protrusion coupled to the first portion via a first side surface. There are other embodiments as well.

Abstract: A DC-DC regulator system includes a power circuit which has a first input coupled to receive an input voltage, a second input coupled to receive a control signal and an output to provide a regulated output voltage. The system includes a control circuit which has a first input coupled to receive the regulated output voltage, a second input coupled to receive a reference voltage, a first output to provide the control signal, and a second output to provide a converter clock signal. The system includes an out-of-audio circuit which has a first input coupled to receive a minimum threshold frequency signal, a second input coupled to receive the converter clock signal, a third input coupled to the power circuit output, and a fourth input coupled to receive a bandwidth control clock signal.

Abstract: An integrated circuit (IC) package includes a one or more die and an interposer. The interposer is coupled to the die and includes circuit traces. The circuit traces are provided in a serpentine configuration. A method can be used to fabricate an integrated circuit package. The method can use an interposer circuit traces having a configuration that allows the circuit traces to deform under stress, and return to an original state undamaged more readily than a straight conductive trace.

Abstract: An apparatus includes a substrate that includes one or more routing layers, and an optical module coupled to the substrate. The optical module includes a photonic integrated circuit (PIC) and electronic integrated circuit (EIC), wherein the photonic integrated circuit is at least partially embedded within the substrate. The apparatus further includes a fiber optic coupler coupled to at least one of the substrate or PIC, wherein the PIC is configured to transmit or receive an optical signal via the fiber optic coupler.

Abstract: A substrate with differing dielectric constant materials is provided. The substrate includes a first ground plane, a second ground plane, a first conductive trace, a first material having a first dielectric constant, and a second material having a second dielectric constant. The first material is disposed between the first ground plane and the first conductive trace, and the second material is disposed between the second ground plane and at least part of the first conductive trace. The first dielectric constant is different from the second dielectric constant.

Abstract: The present disclosure pertains to a system configured to prepare and use prediction models for socioeconomic data and missing value prediction. Some embodiments may: extract, from received population segment data, a training set of socioeconomic parameter values for each population segment; provide, to a prediction model as input, first parameter values of the respective training set for the prediction of additional parameter values of the training set such that the prediction of the additional parameter values is performed without reliance on the additional parameter values; provide, for each of the training sets, the additional parameter values to the prediction model as reference feedback for the prediction model's prediction of the additional parameter values to train the prediction model; and predict, based on a working set of parameter values for a population segment, additional values for the working set using the prediction model subsequent to its training.

Abstract: A semiconductor device with a hybrid bonded interface having microfluidic channels is provided. The semiconductor device includes a first die comprising a first passivation layer, wherein the first passivation layer includes one or more first trenches, and a second die comprising a second passivation layer, wherein the second passivation layer includes one or more second trenches. The first die is bonded to the second die via hybrid copper-to-copper bonding, wherein the one or more first trenches and the one or more second trenches form one or more channels.

Abstract: An apparatus includes a substrate that includes one or more routing layers, and an optical module coupled to the substrate. The optical module includes a photonic integrated circuit (PIC) and electronic integrated circuit (EIC), wherein the photonic integrated circuit is at least partially embedded within the substrate. The apparatus further includes a fiber optic coupler coupled to at least one of the substrate or PIC, wherein the PIC is configured to transmit or receive an optical signal via the fiber optic coupler.

Abstract: Novel tools and techniques are provided for implementing a substrate with an elastomer layer. The substrate might include one or more interconnects and an elastomer layer comprising at least one conductor. In some instances, the at least one conductor of the elastomer layer couples to at least one of the one or more interconnects of the substrate. Additionally, the at least one conductor is configured to couple at least one of the one or more interconnects of the substrate to a circuit board.

Abstract: Novel tools and techniques are provided for implementing edge seal for bonded stacks of different size semiconductor devices. In various embodiments, a semiconductor device is provided that includes a composite structure and a sealant material. The composite structure includes two or more semiconductor devices that form a stacked configuration with one semiconductor device being disposed on or over each of one or more other semiconductor devices (of different size compared with that of the one semiconductor device) and with interface components of the one semiconductor device being bonded with corresponding interface components to each of the one or more other semiconductor devices in the stacked configuration. The sealant material is disposed along one or more surface portions of the composite structure to cover a region including at least portions of side surfaces of the composite structure that extend to cover at least each interface portion between stacked semiconductor devices.

Abstract: Tools and techniques for a semiconductor package providing side wall interconnections are provided. An apparatus includes two or more die layers that are bonded together, the first 3D stacked die package comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes two or more side wall pads, wherein each side wall pad of the two or more side wall pads is coupled to an interconnect of a respective die layer of the two or more die layers.

Abstract: A semiconductor package with integrated side wall antennas is provided. An apparatus includes two or more die layers that are bonded together, each of the two or more die layers comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes a first antenna array, the first antenna array comprising a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements is at least partially exposed at the first side wall.

Abstract: Novel tools and techniques are provided for implementing novel semiconductor package interconnection structure(s) between package substrate and PCB. In various embodiments, a semiconductor device comprises: a substrate; a plurality of posts; a plurality of solder anchor portions; and a plurality of solder balls. Each post is coupled at a proximal end to a conductive point on a layer of the substrate, and has a length extending along its axis between its proximal and distal ends and a width orthogonal to the length. Each solder anchor portion is coupled to the distal end of a corresponding post, and has a width that is larger than the width of a distal end of a pillar portion of the corresponding post. Each solder ball is disposed on and around a corresponding solder anchor portion, the solder balls and corresponding posts forming conductive interconnects between corresponding substrate conductive points and corresponding PCB contact points.