Abstract: A compute in-memory architecture comprising multiple neurons is provided. Each neuron includes one or more storage compute cells, each of which includes a logic circuit configured to receive a multi-bit input and a weight. The weight is defined by one or more weight bits. The logic circuit is further configured to output a control voltage corresponding to logic ‘HIGH’ when XNOR operation between an input sign bit and a corresponding weight bit is 1 and a corresponding input magnitude bit is also 1. A first digital-to-analog converter is formed from a first MOSCAP group in electrical communication with the logic circuit. The first MOSCAP group includes a total number of MOSCAPs equal to input magnitude bit resolution times weight bit resolution. Characteristically, each MOSCAP in the first MOSCAP group has a first end that receives the control voltage, and a second end in electrical communication with a first summation line.