Patents by Inventor Rhett T. Brewer
Rhett T. Brewer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10734491Abstract: Memory devices might include an array of memory cells and a control logic to control access of the array of memory cells, where a memory cell of the array of memory cells might include a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, wherein the charge storage structure comprises a charge-storage material and a gettering agent.Type: GrantFiled: August 8, 2018Date of Patent: August 4, 2020Assignee: Micron Technology, Inc.Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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Publication number: 20180350930Abstract: Memory devices might include an array of memory cells and a control logic to control access of the array of memory cells, where a memory cell of the array of memory cells might include a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, wherein the charge storage structure comprises a charge-storage material and a gettering agent.Type: ApplicationFiled: August 8, 2018Publication date: December 6, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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Patent number: 10074724Abstract: Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic to control access of the array of memory cells, wherein the array of memory cells includes a memory cell having a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, and wherein the charge storage structure includes a charge-storage material and a gettering agent.Type: GrantFiled: November 15, 2016Date of Patent: September 11, 2018Assignee: Micron Technology, Inc.Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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Publication number: 20170062577Abstract: Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic to control access of the array of memory cells, wherein the array of memory cells includes a memory cell having a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, and wherein the charge storage structure includes a charge-storage material and a gettering agent.Type: ApplicationFiled: November 15, 2016Publication date: March 2, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses
Patent number: 9576805Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.Type: GrantFiled: March 24, 2015Date of Patent: February 21, 2017Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Matthew N. Rocklein, Rhett T. Brewer -
Patent number: 9105665Abstract: Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.Type: GrantFiled: May 29, 2014Date of Patent: August 11, 2015Assignee: Micron Technology, Inc.Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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FORTIFICATION OF CHARGE-STORING MATERIAL IN HIGH-K DIELECTRIC ENVIRONMENTS AND RESULTING APPARATUSES
Publication number: 20150200101Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.Type: ApplicationFiled: March 24, 2015Publication date: July 16, 2015Inventors: D.V. Nirmal Ramaswamy, Matthew N. Rocklein, Rhett T. Brewer -
Publication number: 20140264526Abstract: Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.Type: ApplicationFiled: May 29, 2014Publication date: September 18, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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Patent number: 8748964Abstract: Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.Type: GrantFiled: October 22, 2010Date of Patent: June 10, 2014Assignee: Micron Technology, Inc.Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses
Patent number: 8288811Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.Type: GrantFiled: March 22, 2010Date of Patent: October 16, 2012Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Matthew N. Rocklein, Rhett T. Brewer -
Patent number: 8228743Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: GrantFiled: February 10, 2011Date of Patent: July 24, 2012Assignee: Micron Technology, Inc.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Nirmal Ramaswamy, Ronald A Weimer, Arup Bhattacharyya
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Publication number: 20120098047Abstract: Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.Type: ApplicationFiled: October 22, 2010Publication date: April 26, 2012Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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Publication number: 20110133268Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: ApplicationFiled: February 10, 2011Publication date: June 9, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D.V. Nirmal Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Patent number: 7898850Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: GrantFiled: October 12, 2007Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Nirmal Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Publication number: 20090097320Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: ApplicationFiled: October 12, 2007Publication date: April 16, 2009Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Publication number: 20090001443Abstract: Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Applicant: INTEL CORPORATIONInventors: Tejas Krishnamohan, Krishna Parat, Kyu Min, Rhett T. Brewer, Thomas M. Graettinger, Nirmal Ramaswamy, M. Noel Rocklein