Abstract: A method and system for efficiently generating parameterized bus transactions for verification of a design-under-test (DUT) comprises providing a configuration file for the DUT to a generator program. The configuration file defines possible parameter combinations for bus transactions executable by the DUT, and the generator program systematically enumerates all the possible combinations to produce a test case for verifying the DUT. Rules specified within the configuration file can include or exclude selected parameter combinations to tailor the test case to a specific DUT-to-bus interface.

Abstract: A method and system for automating the creation of test cases for logic designs. A comprehensive set of bus transactions characterizing a bus architecture is provided to a test case designer in a user interface. The designer may enter inputs corresponding to a particular design-under-test (DUT) via the interface. The interface processes the inputs to automatically generate a configuration file corresponding to the particular DUT. The configuration file may be processed by a generator program to automatically generate a test case comprising one or more bus transactions customized to the particular DUT.

Abstract: Disclosed is a method and apparatus for optimizing communication between buses operating at different frequencies. A high speed bus provides communication between high speed devices as well as provides communication to a lower speed bus which provides communications between low speed devices and between low speed devices and high speed devices. During transaction reset a bridge device that controls communication between the high and low speed buses determines the ratio of the respective bus clocks. The bridge device sets a logic state machine based on this data and selects from the higher frequency clock selected cycles on which transfers to the lower speed bus take place. The unused cycles of the high speed clock may then be used on the high speed bus for additional transfers. The clock ratios may be determined on each transaction reset and new data on clock ratios stored in the bridge device for subsequent operation.