Patents by Inventor Ria Someshwar
Ria Someshwar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154018Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Applicant: Applied Materials, Inc.Inventors: Ria Someshwar, Seshadri Ganguli, Lan Yu, Siddarth Krishnan, Srinivas Gandikota, Jacqueline S. Wrench, Yixiong Yang
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Patent number: 11908914Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.Type: GrantFiled: July 15, 2021Date of Patent: February 20, 2024Assignee: Applied Materials, Inc.Inventors: Ria Someshwar, Seshadri Ganguli, Lan Yu, Siddarth Krishnan, Srinivas Gandikota, Jacqueline S. Wrench, Yixiong Yang
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Publication number: 20230299236Abstract: Exemplary semiconductor structures may include a silicon-containing substrate. The structures may include a first layer of a first metal nitride overlying the silicon-containing substrate. The structures may include a second layer of a second metal nitride overlying the first layer of the first metal nitride. The structures may include a gallium nitride structure overlying the layer of the metal nitride.Type: ApplicationFiled: March 15, 2022Publication date: September 21, 2023Applicant: Applied Materials, Inc.Inventors: Michel Khoury, Ria Someshwar
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Publication number: 20230117013Abstract: Exemplary semiconductor structures may include a silicon-containing substrate. The structures may include a layer of a metal nitride overlying the silicon-containing substrate. The structures may include a gallium nitride structure overlying the layer of the metal nitride. The structures may include an oxygen-containing layer disposed between the layer of the metal nitride and the gallium nitride structure.Type: ApplicationFiled: October 21, 2021Publication date: April 20, 2023Applicant: Applied Materials, Inc.Inventors: Michel Khoury, Ria Someshwar
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Publication number: 20230124414Abstract: Exemplary semiconductor structures may include a silicon-containing substrate. The structures may include a layer of a metal nitride overlying the silicon-containing substrate. The layer of the metal nitride may include a plurality of features. The structures may include a gallium nitride structure overlying the layer of the metal nitride.Type: ApplicationFiled: March 16, 2022Publication date: April 20, 2023Applicant: Applied Materials, Inc.Inventors: Michel Khoury, Ria Someshwar
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Publication number: 20230115980Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may include a nitrogen-containing nucleation layer deposited on the substrate. The methods may include forming a silicon-containing material on at least a first portion of the nitrogen-containing nucleation layer. The methods may include forming a second layer of material on at least a second portion of the nitrogen-containing nucleation layer. The methods may include forming a masking layer on a portion of the second layer of material. The masking layer may cover less than or about 90% of the second layer of material. The methods may include growing the second layer of material through the masking layer. The methods may include coalescing the second layer of material above the masking layer.Type: ApplicationFiled: October 11, 2021Publication date: April 13, 2023Applicant: Applied Materials, Inc.Inventors: Michel Khoury, Ria Someshwar
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Publication number: 20230015781Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.Type: ApplicationFiled: July 15, 2021Publication date: January 19, 2023Applicant: Applied Materials, Inc.Inventors: Ria Someshwar, Seshadri Ganguli, Lan Yu, Siddarth Krishnan, Srinivas Gandikota, Jacqueline S. Wrench, Yixiong Yang
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Publication number: 20220319836Abstract: Exemplary processing methods include forming a nucleation layer on a substrate. The nucleation layer may be formed by physical vapor deposition (PVD), and the physical vapor deposition may be characterized by a deposition temperature of greater than or about 700° C. The methods may further include forming a patterned mask layer on the nucleation layer. The patterned mask layer may include openings that expose portions of the nucleation layer. Gallium-and-nitrogen-containing regions may be formed on the exposed portions of the nucleation layer. In additional embodiments, the nucleation layer may include a first and second portion separated by an interlayer that stop the propagation of at least some dislocations in the nucleation layer.Type: ApplicationFiled: March 17, 2022Publication date: October 6, 2022Applicant: Applied Materials, Inc.Inventors: Michael Chudzik, Ria Someshwar, Daniel Deyo, Michel Khoury, Sha Zhao
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Patent number: 11362275Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.Type: GrantFiled: April 22, 2020Date of Patent: June 14, 2022Assignee: Applied Materials, Inc.Inventors: Nicolas Louis Gabriel Breil, Siddarth Krishnan, Shashank Sharma, Ria Someshwar, Kai Ng, Deepak Kamalanathan
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Publication number: 20200357993Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.Type: ApplicationFiled: April 22, 2020Publication date: November 12, 2020Applicant: Applied Materials, Inc.Inventors: Nicolas Louis Gabriel Breil, Siddarth Krishnan, Shashank Sharma, Ria Someshwar, Kai Ng, Deepak Kamalanathan
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Publication number: 20200106012Abstract: Exemplary methods of forming a nickel-containing film may include simultaneously flowing a nickel-containing precursor and an oxygen-containing precursor into a semiconductor processing chamber. The methods may include forming a first layer of a nickel-and-oxygen-containing film overlying a substrate housed within the semiconductor processing chamber. The methods may include halting the simultaneous flow. The methods may include flowing a first precursor selected from the nickel-containing precursor and the oxygen-containing precursor into the semiconductor processing chamber. The methods may include flowing a second precursor selected from the nickel-containing precursor and the oxygen-containing precursor into the semiconductor processing chamber. The second precursor may be different from the first precursor. The methods may also include forming a second layer of the nickel-and-oxygen-containing film overlying the first layer of the nickel-and-oxygen-containing film.Type: ApplicationFiled: September 26, 2019Publication date: April 2, 2020Applicant: Applied Materials, Inc.Inventors: Hung Nguyen, Liqi Wu, Feng Q. Liu, Jeffery W. Anthis, Ria Someshwar, Nicolas Louis Gabriel Breil