Abstract: A resonant clocking system for reducing wideband series resonant clock skew is provided. The resonant clocking system includes at least one Pulsed Series Resonance (PSR) driver, at least one clock gater, and at least one clock buffer. The PSR driver is connected with at least one on-chip inductor. The PSR driver receives a boosted-amplitude pulsed signal VSR that is generated using a matching pulse generator and at least one on-chip inductor connected with the at least one Pulsed Series Resonance (PSR) driver resonates with a capacitance of the resonant clocking system to generate a pulse signal RCLK. The at least one clock gater and the at least one clock buffer propagate the pulse signal RCLK to clock pins of resonant flip-flops.

Abstract: Systems and methods of graph-based vehicular intrusion detection are disclosed. According to an aspect, an intrusion detection system includes a computing device configured to receive messages communicated on a vehicular communications network. The computing device also includes construct a set of graphs based on the received messages. Further, the computing device includes apply a graph-based anomaly detection technique to the set of graphs for identifying an anomaly among one or more of the received messages. The computing device also includes implement a predetermined action to mitigate an intrusion based on identification of the anomaly.

Abstract: A resonant clocking system for reducing wideband series resonant clock skew is provided. The resonant clocking system includes at least one Pulsed Series Resonance (PSR) driver, at least one clock gater, and at least one clock buffer. The PSR driver is connected with at least one on-chip inductor. The PSR driver receives a boosted-amplitude pulsed signal VSR that is generated using a matching pulse generator and at least one on-chip inductor connected with the at least one Pulsed Series Resonance (PSR) driver resonates with a capacitance of the resonant clocking system to generate a pulse signal RCLK. The at least one clock gater and the at least one clock buffer propagate the pulse signal RCLK to clock pins of resonant flip-flops.

Abstract: Systems and methods of graph-based vehicular intrusion detection are disclosed. According to an aspect, an intrusion detection system includes a computing device configured to receive messages communicated on a vehicular communications network. The computing device also includes construct a set of graphs based on the received messages. Further, the computing device includes apply a graph-based anomaly detection technique to the set of graphs for identifying an anomaly among one or more of the received messages. The computing device also includes implement a predetermined action to mitigate an intrusion based on identification of the anomaly.

Abstract: Systems and methods for a hybrid current-mode to voltage-mode integrated circuit. An example integrated circuit embodiment configured according to this disclosure can include: a clock circuit and a logic circuit operatively synchronized with said clock circuit, where the logic circuit has a plurality of sub-circuits. The clock circuit can include a current-mode network tree and a plurality of current-mode-to-voltage-mode converters, each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being electrically connected to the current-mode network tree, and each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being associated with a respective one of the plurality of sub-circuits.

Abstract: Systems and methods for a hybrid current-mode to voltage-mode integrated circuit. An example integrated circuit embodiment configured according to this disclosure can include: a clock circuit and a logic circuit operatively synchronized with said clock circuit, where the logic circuit has a plurality of sub-circuits. The clock circuit can include a current-mode network tree and a plurality of current-mode-to-voltage-mode converters, each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being electrically connected to the current-mode network tree, and each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being associated with a respective one of the plurality of sub-circuits.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.