Patents by Inventor Riadul Islam

Riadul Islam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS OF GRAPH-BASED VEHICULAR INTRUSION DETECTION
    Publication number: 20220377094
    Abstract: Systems and methods of graph-based vehicular intrusion detection are disclosed. According to an aspect, an intrusion detection system includes a computing device configured to receive messages communicated on a vehicular communications network. The computing device also includes construct a set of graphs based on the received messages. Further, the computing device includes apply a graph-based anomaly detection technique to the set of graphs for identifying an anomaly among one or more of the received messages. The computing device also includes implement a predetermined action to mitigate an intrusion based on identification of the anomaly.
    Type: Application
    Filed: April 5, 2022
    Publication date: November 24, 2022
    Inventor: Riadul Islam
  • System and method for a hybrid current-mode and voltage-mode integrated circuit
    Patent number: 10691162
    Abstract: Systems and methods for a hybrid current-mode to voltage-mode integrated circuit. An example integrated circuit embodiment configured according to this disclosure can include: a clock circuit and a logic circuit operatively synchronized with said clock circuit, where the logic circuit has a plurality of sub-circuits. The clock circuit can include a current-mode network tree and a plurality of current-mode-to-voltage-mode converters, each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being electrically connected to the current-mode network tree, and each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being associated with a respective one of the plurality of sub-circuits.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: June 23, 2020
    Assignee: The Regents of the University of California
    Inventors: Matthew Guthaus, Riadul Islam
  • SYSTEM AND METHOD FOR A HYBRID CURRENT-MODE AND VOLTAGE-MODE INTEGRATED CIRCUIT
    Publication number: 20190384349
    Abstract: Systems and methods for a hybrid current-mode to voltage-mode integrated circuit. An example integrated circuit embodiment configured according to this disclosure can include: a clock circuit and a logic circuit operatively synchronized with said clock circuit, where the logic circuit has a plurality of sub-circuits. The clock circuit can include a current-mode network tree and a plurality of current-mode-to-voltage-mode converters, each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being electrically connected to the current-mode network tree, and each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being associated with a respective one of the plurality of sub-circuits.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Inventors: Matthew Guthaus, Riadul Islam
  • Current-mode clock distribution
    Patent number: 10097168
    Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 9, 2018
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Matthew Guthaus, Riadul Islam
  • CURRENT-MODE CLOCK DISTRIBUTION
    Publication number: 20180076799
    Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 15, 2018
    Applicant: The Regents of the University of California
    Inventors: Matthew Guthaus, Riadul Islam
  • Current-mode clock distribution
    Patent number: 9787293
    Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: October 10, 2017
    Assignee: Regents of the University of California
    Inventors: Matthew Guthaus, Riadul Islam
  • CURRENT-MODE CLOCK DISTRIBUTION
    Publication number: 20170012614
    Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.
    Type: Application
    Filed: January 29, 2015
    Publication date: January 12, 2017
    Applicant: The Regents of the University of California
    Inventors: Matthew Guthaus, Riadul Islam