Abstract: A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score. The method further includes providing the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.

Abstract: A processing device receives one or more inputs for design verification of an integrated circuit using an emulation compiler. The processing device determines a type of compiler for processing the one or more inputs. In response to determining that the type of compiler is a simulation compiler, the processing device modifies the simulation compiler according to the one or more inputs to form a modified simulation compiler to match one or more emulation semantics associated with the emulation compiler. The processing device performs a design verification using the modified simulation compiler.

Abstract: Embodiments relate to a system and method for analyzing strongly connected components (SCCs) in a design of an integrated circuit. In one embodiment, a design of an integrated circuit is received, and a set of loops are identified in the received design. Based on the identified loops, one or more SCCs are determined. Each SCC includes multiple loops having shared paths. For instance, an SCC includes a first loop having a first set of nodes connected via a first set of paths and a second loop having a second set of nodes connected via a second set of paths, such that the first loop and the second loop have at least one path in common. The identified SCCs are then analyzed and presented to the user for consideration when reviewing the design of the integrated circuit.

Abstract: A configuration for testing a design of an electronic circuit during a set of clock cycles. The test output of the emulation of a design is filtered based on a received testcase. To filter the test output, for each clock cycle in the testcase, a list of objects associated with a previous clock cycle in test case is identified. One or more objects associated with the one or more commands to be executed during the clock cycle is also identified. An updated list is generated by augmenting the list of objects associated with the previous clock cycle with the one or more objects associated with the one or more commands to be executed during the clock cycle. Output values for objects included in the updated list of objects is selected. The filtered test output is then stored in an activity database.

Abstract: A configuration for testing a design of an electronic circuit during a set of clock cycles. The test output of the emulation of a design is filtered based on a received testcase. To filter the test output, for each clock cycle in the testcase, a list of objects associated with a previous clock cycle in test case is identified. One or more objects associated with the one or more commands to be executed during the clock cycle is also identified. An updated list is generated by augmenting the list of objects associated with the previous clock cycle with the one or more objects associated with the one or more commands to be executed during the clock cycle. Output values for objects included in the updated list of objects is selected. The filtered test output is then stored in an activity database.