Abstract: Techniques regarding microwave-to-optical quantum transducers are provided. For example, one or more embodiments described herein can include an apparatus that can include a microwave resonator on a dielectric substrate and adjacent to an optical resonator, and a photon barrier structure at least partially surrounding an optical resonator, wherein the photon barrier structure is configured to provide isolation of the microwave resonator from optical photons in the dielectric substrate outside the photon barrier structure.

Abstract: Techniques regarding microwave-to-optical quantum transducers are provided. For example, one or more embodiments described herein can include an apparatus that can include a microwave resonator on a dielectric substrate and adjacent to an optical resonator, and a photon barrier structure at least partially surrounding an optical resonator, wherein the photon barrier structure is configured to provide isolation of the microwave resonator from optical photons in the dielectric substrate outside the photon barrier structure.

Abstract: A die stack that includes a first chip die, a second chip die connected to the first chip die by one or more controlled collapse chip connection (“C4”) solder bump bonds, and a spacer die interposed between the first and second chip dies. The spacer die includes through holes for the one or more C4 solder bumps, and has a thickness such that when the first and second chip dies are compressed into contact with the spacer die, the spacer die thickness is a minimum defined spacing between the first and second chip dies, and the spacer die operates as a hard stop against compression of the die stack after the first and second chip dies are compressed into contact with the spacer die.

Abstract: An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

Abstract: Semiconductor device structures and fabrication methods for field effect transistors in which a gate electrode is provided with an air gap or void disposed adjacent to a sidewall of the gate electrode. The void may be bounded by a dielectric spacer proximate to the sidewall of the gate electrode and a dielectric layer having a spaced relationship with the dielectric spacer. The methods of the invention involve the use of a temporary spacer consisting of a sacrificial material supplied adjacent to the sidewall of the gate electrode, which is removed after the dielectric layer is formed.

Abstract: An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

Abstract: A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.

Abstract: Semiconductor device structures and fabrication methods for field effect transistors in which a gate electrode is provided with an air gap or void disposed adjacent to a sidewall of the gate electrode. The void may be bounded by a dielectric spacer proximate to the sidewall of the gate electrode and a dielectric layer having a spaced relationship with the dielectric spacer. The methods of the invention involve the use of a temporary spacer consisting of a sacrificial material supplied adjacent to the sidewall of the gate electrode, which is removed after the dielectric layer is formed.

Abstract: The present invention relates to methods for controlling the etching rate of CoSi2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schotky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.

Abstract: The present invention relates to methods for controlling the etching rate of CoSi.sub.2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schottky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.