Patents by Inventor Ricardo Ascazubi

Ricardo Ascazubi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220221510
    Abstract: Laser-based integrated circuit (IC) device testing apparatus capable of inducing localized regions of high temperature within an IC device under test (DUT). A laser source of sufficiently high output power (e.g., 1 W) within an output band that has an energy less than that of a bandgap of one or more semiconductor materials within the DUT may heat a target portion of the DUT proximal to active devices. High levels of thermal stress are possible with the ability to induce temperatures of 300° C., or more. High spatial resolution of thermal stress with the DUT is possible with laser beam spot diameters of less than 4 ?m. Accelerated aging tests and thermal sensitivity characterizations of a DUT may be implemented with laser-based heating to expand the range of possible testing conditions and/or generate more precise test data at a more rapid pace.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Applicant: Intel Corporation
    Inventors: Ricardo Ascazubi, Georgia Modoran
  • Publication number: 20220187362
    Abstract: Laser-assisted integrated circuit (IC) device testing apparatus capable of inducing hot carrier injection (HCI) within selected transistors of an IC device. A laser source of sufficiently high output power (e.g., 1W) and short pulse duration (e.g., 100 fs) can generate enough hot carriers through a multi-photon (e.g., TPA) carrier injection mechanism to significantly accelerate HCI aging even at low transistor voltage bias (e.g., <1.5V). Rapid laser-assisted HCI transistor aging can selectively degrade transistors of individual functional IC blocks within an IC device.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 16, 2022
    Applicant: Intel Corporation
    Inventors: Ricardo Ascazubi, Georgia Modoran
  • Publication number: 20180181876
    Abstract: Various implementations provide an aquatic conditions optimization management system accesses aquatic sensor data generated by one or more aquatic sensors, identifies a collection of aquatic data that includes data generated by and collected from the aquatic sensor(s), generates a set of cross-correlation matrices based on the collection of aquatic data, executes a set of unsupervised machine learning algorithms using the set of cross-correlation matrices, and determines one or more optimum conditions for one or more aquatic resources based on the executed set of unsupervised machine learning algorithms. The optimum condition(s) may be communicated to one or more individuals and may include one or more corrective actions to improve one or more of the aquatic resources.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Applicant: Intel Corporation
    Inventors: Keenan Zhuo, Suraj Sindia, Ricardo Ascazubi, Balkaran Gill, Clark VanDam
  • Patent number: 9819258
    Abstract: Systems and methods for latch-up detection and mitigation. One aspect includes a method implemented in a system divided into a plurality of power blocks, where each power block is powered by a corresponding power rail and includes a voltage droop monitoring circuitry. The method comprises receiving frequency information from the plurality of voltage droop monitoring circuitries; normalizing the received frequency information from each of the plurality of voltage droop monitoring circuitries; creating a matrix of cross-correlation values based on the normalized frequency information between each pair of the plurality of power blocks; determining deviations in the cross-correlation values indicating an occurrence of voltage droop; determining an abnormal variation based on the determined deviations to identify a first power block, out of the plurality of power blocks, experiencing a latch-up event; and resetting power to the first power block without interrupting power to rest of the plurality of power blocks.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Clark Vandam, Suriya Kumar, Suraj Sindia, Ricardo Ascazubi, Curtis Shirota