Patents by Inventor Ricardo H. Bruce
Ricardo H. Bruce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10877907Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.Type: GrantFiled: November 20, 2018Date of Patent: December 29, 2020Assignee: BITMICRO LLCInventors: Ricardo H. Bruce, Elsbeth Lauren Tagayo Villapana, Joel Alonzo Baylon
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Patent number: 10552050Abstract: In an embodiment of the invention, an apparatus comprises: a multi-dimensional memory that is expandable in a first direction; wherein the multi-dimensional memory comprises a serial chain; wherein the serial chain comprises a first serial chain that is expandable in a first direction; and wherein the first serial chain comprises a first memory controller, a first memory module coupled to the first memory controller, a second memory controller coupled to the first memory controller, and a second memory module coupled to the second memory controller.Type: GrantFiled: April 7, 2017Date of Patent: February 4, 2020Assignee: BiTMICRO LLCInventors: Marlon B. Verdan, Ricardo H. Bruce
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Patent number: 10489318Abstract: In an embodiment of the invention, an apparatus comprises: a first flash module comprising a first flash device; and a second flash module comprising a second flash device; wherein the first flash module and second flash module are coupled by a flash interconnect; wherein the first flash device is configured to store a first data stripe of a data and wherein the second flash device is configured to store a second data stripe of the data. In another embodiment of the invention, a method comprises: storing, in a first flash device in a first flash module, a first data stripe of a data; and storing, in a second flash device in a second flash module, a second data stripe of the data; wherein the first flash module and second flash module are coupled by a flash interconnect.Type: GrantFiled: April 17, 2015Date of Patent: November 26, 2019Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Avnher Villar Santos, Marlon Basa Verdan, Elsbeth Lauren Tagayo Villapana
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Patent number: 10459842Abstract: In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.Type: GrantFiled: February 24, 2018Date of Patent: October 29, 2019Assignee: BiTMICRO Networks, Inc.Inventors: Rey H. Bruce, Ricardo H. Bruce, Marlon B. Verdan, Elsbeth Lauren Tagayo-VillapaƱa
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Patent number: 10430303Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.Type: GrantFiled: February 7, 2018Date of Patent: October 1, 2019Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Cyrill Coronel Ponce, Jarmie Dela Cruz Espuerta, Marlon Basa Verdan
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Patent number: 10423554Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.Type: GrantFiled: October 23, 2017Date of Patent: September 24, 2019Assignee: BiTMICRO Networks, IncInventors: Ricardo H. Bruce, Cyrill Coronel Ponce, Jarmie Dela Cruz Espuerta
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Publication number: 20190087363Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.Type: ApplicationFiled: November 20, 2018Publication date: March 21, 2019Applicant: BITMICRO LLCInventors: Ricardo H. Bruce, Elsbeth Lauren Tagayo Villapana, Joel Alonzo Baylon
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Patent number: 10133686Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.Type: GrantFiled: June 6, 2014Date of Patent: November 20, 2018Assignee: BiTMICRO LLCInventors: Ricardo H. Bruce, Elsbeth Lauren Tagayo Villapana, Joel Alonzo Baylon
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Patent number: 10120586Abstract: A solution for performing reduced latency memory read transactions is disclosed. In one example, a storage apparatus has a memory array that includes: a flash device having a data register, a memory interface coupled to the memory array and a buffer set that includes at least one buffer suitable for use as a prefetch buffer. The memory interface, in response to a memory read transaction request, performs a read operation and, if stored data exists within the memory array that meets a prefetch selection criterion, also performs an internal read operation. The internal read operation includes allocating a prefetch buffer in the buffer set and storing the data as prefetch data in the prefetch buffer. If the memory interface receives a second memory read transaction request for data that is currently available as prefetch data, the memory interface responds by performing a forwarding transaction that includes retrieving the prefetch data from the prefetch buffer and forwarding the prefetch data to a host.Type: GrantFiled: February 7, 2015Date of Patent: November 6, 2018Assignee: BiTMICRO, LLCInventors: Rey H. Bruce, Ricardo H. Bruce, Elsbeth Lauren Tagayo-Villapana
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Patent number: 10013373Abstract: In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.Type: GrantFiled: November 6, 2016Date of Patent: July 3, 2018Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Bernard Sherwin Leung Chiw, Margaret Anne Nadonga Somera
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Patent number: 9971524Abstract: An embodiment of the invention provides a method for optimizing flash device accesses, comprising: interleaving and striping, in tandem, for a transfer of data the other portions of the data.Type: GrantFiled: March 17, 2014Date of Patent: May 15, 2018Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Avnher Villar Santos, Marlon Basa Verdan, Elsbeth Lauren Tagayo Villapana
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Patent number: 9952991Abstract: In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors.Type: GrantFiled: April 17, 2015Date of Patent: April 24, 2018Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Marlon B. Verdan, Rowenah Michelle Jago-on
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Patent number: 9916213Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.Type: GrantFiled: April 16, 2015Date of Patent: March 13, 2018Assignee: BITMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Cyrill Coronel Ponce, Jarmie De La Cruz Espuerta, Marlon Basa Verdan
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Patent number: 9875205Abstract: A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.Type: GrantFiled: March 17, 2014Date of Patent: January 23, 2018Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Jarmie De La Cruz Espuerta, Marlon Basa Verdan
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Patent number: 9798688Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.Type: GrantFiled: March 17, 2014Date of Patent: October 24, 2017Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Cyrill Coronel Ponce, Jarmie Dela Cruz Espuerta
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Patent number: 9501436Abstract: In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.Type: GrantFiled: March 17, 2014Date of Patent: November 22, 2016Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Bernard Sherwin Leung Chiw, Margaret Anne Nadonga Somera
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Patent number: 9135190Abstract: The present invention pertains to a multi-profile memory controller and devices that use multi-profile memory controllers. More particularly, the present invention pertains to a multi-profile memory controller and related methods and systems that can operate with memory locations, memory devices, or both which are associated with different memory attributes, different attribute qualifiers, or the like, while minimizing or avoiding some or all of the disadvantages of the prior art.Type: GrantFiled: September 4, 2010Date of Patent: September 15, 2015Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Marlon B. Verdan, Margaret Anne N. Somera, Rowenah Michelle D. Jago-on, Maria Eliza B. De Belen, Ron Kelvin B. Palacol
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Patent number: 8959307Abstract: A solution for performing reduced latency memory read transactions is disclosed. In one example, a storage apparatus has a memory array that includes: a flash device having a data register, a memory interface coupled to the memory array and a buffer set that includes at least one buffer suitable for use as a prefetch buffer. The memory interface, in response to a memory read transaction request, performs a read operation and, if stored data exists within the memory array that meets a prefetch selection criterion, also performs an internal read operation. The internal read operation includes allocating a prefetch buffer in the buffer set and storing the data as prefetch data in the prefetch buffer. If the memory interface receives a second memory read transaction request for data that is currently available as prefetch data, the memory interface responds by performing a forwarding transaction that includes retrieving the prefetch data from the prefetch buffer and forwarding the prefetch data to a host.Type: GrantFiled: November 13, 2008Date of Patent: February 17, 2015Assignee: BiTMICRO Networks, Inc.Inventors: Rey H. Bruce, Ricardo H. Bruce, Elsbeth Lauren Tagayo-VillapaƱa
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Publication number: 20140289441Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.Type: ApplicationFiled: June 6, 2014Publication date: September 25, 2014Inventors: Ricardo H. Bruce, Elsbeth Lauren Tagayo Villapana, Joel Alonzo Baylon
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Patent number: 8788725Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.Type: GrantFiled: May 8, 2013Date of Patent: July 22, 2014Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Elsbeth Lauren Tagayo Villapana, Joel Alonzo Baylon