Abstract: An exemplary write method disclosed herein includes receiving a request to write data to a consecutive sequence of logical block addresses (LBAs) that is the mapped to a non-contiguous sequence of data tracks on a storage medium, and writing the data of the consecutive sequence of LBAs to a non-contiguous sequence of data tracks on the storage medium and according to a consecutive track order.

Abstract: A method for generating an integrated circuit (IC) is provided wherein signal delays are transferable across two synthesis libraries where each library is associated with a different IC fabrication process. The method initiates with describing an IC design through a hardware description language (HDL). The method includes identifying logic signal delay points within the HDL. Then, technology-independent logic signal delay code is inserted within the delay points of the HDL representation. A system for designing an IC is also provided.

Abstract: A method and apparatus for burst mode data transfers between a CPU and a FIFO. The CPU executes a burst mode memory access instruction defining multiple memory addresses. The multiple memory addresses are decoded to produce an output that is the same for each of the multiple memory addresses. The FIFO is accessed repeatedly, for each of the multiple addresses, by use of the output.

Abstract: A graphics controller providing flexible access to a graphics display device by a host. The controller includes an input bus for coupling to an output bus of the host, an output bus for coupling to the input bus of the graphics display device, a video processing circuit having an input coupled to the input bus of the graphics controller and an output coupled to the output bus of the graphics controller, and a bypass switching circuit adapted to switchably couple the input bus of the graphics controller to the output bus of the graphics controller so as to bypass the video processing circuit.

Abstract: A peripheral card (109) having an adaptive PCMCIA compliant interface including either an adaptive card present or card configuration function that includes a peripheral apparatus (209) arranged and constructed to operate in conjunction with a host computer (101) over a PCMCIA compliant interface, and an interface logic (205), coupled to the peripheral apparatus (209) and to a PCMCIA peripheral port (201), for interfacing the peripheral apparatus to the PCMCIA peripheral port (201), the interface logic further adaptively providing a card present signal at the PCMCIA peripheral port (201) when the peripheral apparatus (209) and the interface logic (205) expects the PCMCIA peripheral port (201) to be activated by the host computer (101) or alternatively adaptively providing configuration information pertaining to the peripheral apparatus to the host computer.

Abstract: A PCMCIA card having independent functionality and alternatively arranged to operate in conjunction with a host computer, that includes a peripheral apparatus (109) having an integral CPU (125), a power source (129), and a power supply (127) for exhibiting an independent operating state; and an interface function (121) integral with and coupled to said peripheral apparatus (109), said interface function arranged and constructed to couple said peripheral apparatus to the host computer (101) over a PCMCIA compliant interface and initiate a dependent operating state at said peripheral apparatus (109).

Abstract: A data demodulation logic unit (200) and method used therein, adaptable to multiple data protocols, including an arithmetic logic unit (205) that is architecturally optimized to demodulate multiple data protocols under the control of a hardware based state machine (209) that operates in a selectable mode that corresponds to one of multiple data protocols.