Abstract: A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.

Abstract: A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.

Abstract: In some embodiments, a source follower circuit may include a first level shifter configured to receive an input voltage; an N-type Metal-Oxide-Semiconductor (NMOS) transistor having a gate terminal coupled to an output of the first level shifter; a second level shifter configured to receive the input voltage; a P-type Metal-Oxide-Semiconductor (PMOS) transistor having a gate terminal coupled to an output of the second level shifter and a source terminal coupled to a source terminal of the NMOS transistor; and an amplifier configured to receive the input voltage and to output a current at a node between the source terminal of the NMOS transistor and the source terminal of the PMOS transistor, wherein the current is determined based upon a difference between the input voltage and a reference voltage.

Abstract: Systems and methods for production test trimming acceleration. In an illustrative, non-limiting embodiment, a method may include providing a first trim code to a reference circuit, where the reference circuit is configured to output a first signal in response to the first trim code; integrating a difference between the first signal and a target voltage value into a first integrated value; providing a second trim code to the reference circuit, where the reference circuit is configured to output a second signal in response to the second trim code; integrating a difference between the second signal and the target voltage value into a second integrated value; and adjusting at least one of the first or second trim codes in response to a comparison between the first and second integrated values.

Abstract: Systems and methods for production test trimming acceleration. In an illustrative, non-limiting embodiment, a method may include providing a first trim code to a reference circuit, where the reference circuit is configured to output a first signal in response to the first trim code; integrating a difference between the first signal and a target voltage value into a first integrated value; providing a second trim code to the reference circuit, where the reference circuit is configured to output a second signal in response to the second trim code; integrating a difference between the second signal and the target voltage value into a second integrated value; and adjusting at least one of the first or second trim codes in response to a comparison between the first and second integrated values.

Abstract: A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.

Abstract: Metal-Oxide-Semiconductor (MOS) voltage divider with dynamic impedance control. In some embodiments, a voltage divider may include two or more voltage division cells, each voltage division cell having a plurality of Metal-Oxide-Semiconductor (MOS) transistors, a least one of the plurality of MOS transistors connected to a signal path and at least another one of the plurality of MOS transistors connected to a control path, the voltage division cell configured to provide a voltage drop across the signal path based upon a control signal applied to the control path.

Abstract: Rail-to-rail follower circuits. In some embodiments, a source follower circuit may include a first level shifter configured to receive an input voltage; an N-type Metal-Oxide-Semiconductor (NMOS) transistor having a gate terminal coupled to an output of the first level shifter; a second level shifter configured to receive the input voltage; a P-type Metal-Oxide-Semiconductor (PMOS) transistor having a gate terminal coupled to an output of the second level shifter and a source terminal coupled to a source terminal of the NMOS transistor; and an amplifier configured to receive the input voltage and to output a current at a node between the source terminal of the NMOS transistor and the source terminal of the PMOS transistor, wherein the current is determined based upon a difference between the input voltage and a reference voltage.

Abstract: A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.

Abstract: Metal-Oxide-Semiconductor (MOS) voltage divider with dynamic impedance control. In some embodiments, a voltage divider may include two or more voltage division cells, each voltage division cell having a plurality of Metal-Oxide-Semiconductor (MOS) transistors, a least one of the plurality of MOS transistors connected to a signal path and at least another one of the plurality of MOS transistors connected to a control path, the voltage division cell configured to provide a voltage drop across the signal path based upon a control signal applied to the control path.

Abstract: A programmable temperature sensing circuit includes a comparator, first and second CTAT sensing elements, first and second PTAT reference circuits, and a selection circuit. When a selection signal is a first logic state, an output terminal of the first PTAT reference circuit is coupled to the second CTAT temperature sensing element for providing a first threshold voltage to the second input of the comparator. When the selection signal is a second logic state different from the first logic state, a series-connection of the first PTAT reference circuit and the second PTAT reference circuit are coupled to the second CTAT temperature sensing element for providing a second threshold voltage to the second input of the comparator. The comparator provides an output voltage indication when a voltage provided by the first CTAT sensing element compares favorably with the selected one of the first or second threshold voltages.

Abstract: A programmable temperature sensing circuit includes a comparator, first and second CTAT sensing elements, first and second PTAT reference circuits, and a selection circuit. When a selection signal is a first logic state, an output terminal of the first PTAT reference circuit is coupled to the second CTAT temperature sensing element for providing a first threshold voltage to the second input of the comparator. When the selection signal is a second logic state different from the first logic state, a series-connection of the first PTAT reference circuit and the second PTAT reference circuit are coupled to the second CTAT temperature sensing element for providing a second threshold voltage to the second input of the comparator. The comparator provides an output voltage indication when a voltage provided by the first CTAT sensing element compares favorably with the selected one of the first or second threshold voltages.