Patents by Inventor Ricardo P. MIKALO
Ricardo P. MIKALO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10256134Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.Type: GrantFiled: June 9, 2017Date of Patent: April 9, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ricardo P. Mikalo, Martin Gerhardt
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Publication number: 20180358259Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.Type: ApplicationFiled: June 9, 2017Publication date: December 13, 2018Inventors: Ricardo P. Mikalo, Martin Gerhardt
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Patent number: 10147659Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips, which includes forming routing structure(s) that facilitate process limiting yield (PLY) testing of test devices. A routing structure includes an array of link-up regions and a set of metal pads surrounding that array. Each link-up region includes two sections, each having two nodes electrically connected to the terminals of a corresponding two-terminal test device. During PLY testing with a probe card, electrical connections between the test devices and the metal pads through the link-up regions allow each test device to be tested individually. Optionally, additional routing structures with the same footprint are formed down the line and stacked one above the other. These additional routing structures are used for PLY testing with the same probe card. Optionally, dummy pads are formed between stacked routing structures to improve robustness. Also disclosed is a semiconductor structure formed according to this method.Type: GrantFiled: July 18, 2017Date of Patent: December 4, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Uwe Dersch, Ricardo P. Mikalo, Thomas Merbeth
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Patent number: 9093554Abstract: In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.Type: GrantFiled: May 14, 2012Date of Patent: July 28, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Ricardo P. Mikalo, Jan Hoentschel
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Patent number: 9087587Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the second conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate.Type: GrantFiled: March 15, 2013Date of Patent: July 21, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Ricardo P. Mikalo, Stefan Flachowsky
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Publication number: 20140269060Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: Ricardo P. Mikalo, Stefan Flachowsky
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Patent number: 8669170Abstract: Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.Type: GrantFiled: January 16, 2012Date of Patent: March 11, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Ricardo P. Mikalo, Stefan Flachowsky
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Patent number: 8642420Abstract: A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.Type: GrantFiled: August 26, 2011Date of Patent: February 4, 2014Assignee: Globalfoundries, Inc.Inventors: Stefan Flachowsky, Frank Wirbeleit, Matthias Kessler, Ricardo P. Mikalo
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Publication number: 20130302956Abstract: In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.Type: ApplicationFiled: May 14, 2012Publication date: November 14, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Ricardo P. Mikalo, Jan Hoentschel
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Patent number: 8536019Abstract: Apparatus and related fabrication methods are provided for semiconductor device structures having encapsulated isolation regions. An exemplary method for fabricating a semiconductor device structure involves the steps of forming an isolation region of a first dielectric material in the semiconductor substrate adjacent to a first region of the semiconductor material, forming a first layer of a second dielectric material overlying the isolation region and the first region, and removing the second dielectric material overlying the first region leaving portions of the second dielectric material overlying the isolation region intact. The isolation region is recessed relative to the first region, and the second dielectric material is more resistant to an etchant than the first dielectric material.Type: GrantFiled: May 17, 2011Date of Patent: September 17, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Ricardo P. Mikalo, Frank W. Wirbeleit
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Patent number: 8524566Abstract: Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.Type: GrantFiled: December 20, 2011Date of Patent: September 3, 2013Assignee: GlobalFoundries, Inc.Inventors: Stefan Flachowsky, Ricardo P. Mikalo, Jan Hoentschel
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Publication number: 20130207275Abstract: Disclosed herein are various methods of forming device level conductive contacts to improve device performance and various semiconductor devices with such improved deice level contact configurations. In one example, a device disclosed herein includes a first device level conductive contact positioned in a first layer of insulating material, wherein the first device level conductive contact is conductively coupled to a semiconductor device, a second device level conductive contact positioned above and conductively coupled to the first device level contact, wherein the second device level contact is positioned in a second layer of insulating material, and a first wiring layer for the device that is positioned above and conductively coupled to the second device level conductive contact.Type: ApplicationFiled: February 15, 2012Publication date: August 15, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Ricardo P. Mikalo, Thilo Scheiper, Stefan Flachowsky
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Publication number: 20130183817Abstract: Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.Type: ApplicationFiled: January 16, 2012Publication date: July 18, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Ricardo P. Mikalo, Stefan Flachowsky
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Patent number: 8476131Abstract: In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.Type: GrantFiled: August 24, 2011Date of Patent: July 2, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Ralf Illgen, Thilo Scheiper, Ricardo P. Mikalo
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Publication number: 20130157421Abstract: Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Ricardo P. Mikalo, Jan Hoentschel
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Publication number: 20130065367Abstract: In one example, a method disclosed herein includes the steps of forming gate electrode structures for a PMOS transistor and for an NMOS transistor, forming a first spacer proximate the gate electrode structures, after forming the first spacer, forming extension implant regions in the substrate for the transistors and after forming the extension implant regions, forming a second spacer proximate the first spacer for the PMOS transistor. This method also includes performing an etching process with the second spacer in place to define a plurality of cavities in the substrate proximate the gate structure for the PMOS transistor, removing the first and second spacers, forming a third spacer proximate the gate electrode structures of both of the transistors, and forming deep source/drain implant regions in the substrate for the transistors.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Thilo Scheiper, Ricardo P. Mikalo
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Publication number: 20130049126Abstract: In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Ralf Illgen, Thilo Scheiper, Ricardo P. Mikalo
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Publication number: 20130052779Abstract: A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.Type: ApplicationFiled: August 26, 2011Publication date: February 28, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Frank Wirbeleit, Matthias Kessler, Ricardo P. Mikalo
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Publication number: 20120301688Abstract: Devices are formed that combine low resistance for circuit needs with high flexibility for application needs. Embodiments include forming a low resistance layer on a substrate and forming a high flexibility conductive layer on the low resistance layer, wherein the high flexibility conductive layer provides for continuous conductivity of the low resistance layer. Embodiments include forming a pattern in the low resistance and high flexibility conductive layers simultaneously, or forming a pattern in the low resistance layer prior to forming the high flexibility conductive layer.Type: ApplicationFiled: May 25, 2011Publication date: November 29, 2012Applicant: GLOBALFOUNDRIES Inc.Inventors: Ricardo P. MIKALO, Stephan D. KRONHOLZ, Matthias KESSLER
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Publication number: 20120292734Abstract: Apparatus and related fabrication methods are provided for semiconductor device structures having encapsulated isolation regions. An exemplary method for fabricating a semiconductor device structure involves the steps of forming an isolation region of a first dielectric material in the semiconductor substrate adjacent to a first region of the semiconductor material, forming a first layer of a second dielectric material overlying the isolation region and the first region, and removing the second dielectric material overlying the first region leaving portions of the second dielectric material overlying the isolation region intact. The isolation region is recessed relative to the first region, and the second dielectric material is more resistant to an etchant than the first dielectric material.Type: ApplicationFiled: May 17, 2011Publication date: November 22, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Ricardo P. MIKALO, Frank W. WIRBELEIT