Patents by Inventor Ricardo Sedillos Padilla

Ricardo Sedillos Padilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7865783
    Abstract: A method, system and computer program product for logging and identifying microcode errors in a computing environment is provided. Each of a plurality of errors in the microcode is logged using a plurality of error logging commands. Each of the plurality of errors is indexed to generate a plurality of indexed errors. A plurality of unique keys is associated to each of the plurality of indexed errors. A master index of the plurality of unique keys is created.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthew Charles Compton, Louis Daniel Echevarria, Ricardo Sedillos Padilla, Richard Albert Welp
  • Patent number: 7752617
    Abstract: An apparatus, system, and method are provided for updating a code image. The apparatus, system, and method include a loader for loading a new code image into a temporary memory location separate from the memory location occupied by the old code image. A conversion module of the new code image executes and selectively reconciles incompatibilities between the old code image and the new code image. In one aspect, once incompatibilities are reconciled, a copy module copies the new code image into the memory space occupied by the old code image.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stephen La Roux Blinick, Brian Jeffrey Corcoran, Matthew Joseph Kalos, Ricardo Sedillos Padilla
  • Publication number: 20090292955
    Abstract: A method, system and computer program product for logging and identifying microcode errors in a computing environment is provided. Each of a plurality of errors in the microcode is logged using a plurality of error logging commands. Each of the plurality of errors is indexed to generate a plurality of indexed errors. A plurality of unique keys is associated to each of the plurality of indexed errors. A master index of the plurality of unique keys is created.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 26, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew Charles COMPTON, Louis Daniel ECHEVARRIA, Ricardo Sedillos PADILLA, Richard Albert WELP
  • Patent number: 7536694
    Abstract: In one embodiment, a first processor of a multiprocessor system, encounters an exception and jumps to exception handler code at an architecture-defined exception vector. The processor is directed to a data structure which provides a programmable exception vector to additional exception handler code. This additional code may be executed as if it were located at the architecture-defined exception vector. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: Stephen LaRoux Blinick, Ricardo Sedillos Padilla
  • Patent number: 7512616
    Abstract: An apparatus, system, and method are disclosed for communicating binary data using a self-descriptive binary data structure. The binary data structure also may be referred to as a microcode reconstruct and boot (MRB) image. The binary data structure includes a plurality of data segments, a target data set, and a data structure descriptor. Each of the data segments has a data segment header and data field. The target data set is stored within the data field and may be an executable. The data structure descriptor is descriptive of the binary data structure and identifies the location of the target data set within the data field. The binary data structure is self-descriptive in that the location of an individual target data set may be identified by the data structure descriptor.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Brian Jeffrey Corcoran, Lourdes Magally Gee, Matthew Joseph Kalos, Ricardo Sedillos Padilla
  • Patent number: 7313681
    Abstract: An apparatus, system, and method are disclosed for fastload code update on a communications adapter. The apparatus includes an image load module, a memory initialization module, and an image overlay module. The image load module is configured to load a copy of a new code image in a memory on the communications adapter. The memory also concurrently stores a copy of an old code image used by the communications adapter. The memory initialization module is configured to invoke the new code image to perform a memory initialization operation. The memory initialization module may perform the memory initialization operation concurrently with ongoing I/O requests possibly accepted, but not necessarily processed, by the old code image. The image overlay module is configured to overlay the old code image with the new code image. The fastload code update minimizes the time that the communications adapter is off-line to overlay the old code image with the new code image and reinitialize the communications adapter.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: December 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: James Chien-Chiung Chen, Brian Jeffrey Corcoran, Matthew Joseph Kalos, Ricardo Sedillos Padilla