Patents by Inventor Ricardo YANDOC

Ricardo YANDOC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153838
    Abstract: A locking system for a semiconductor device is provided, that includes a locking clip and a lead frame, having a first and a second lead frame surface. The clip has a first and a second locking clip surface and includes a first and a second locking means. The first locking means is structured to align with the second locking means, so that a movement of the locking clip relative to the lead frame is possible in only one direction, and the locking clip is placed on the lead frame, so that the first locking clip surface of the locking clip is in contact with the second lead frame surface. This configuration prevents clip swaying during assembly and maximizes the use of copper material for both clips and lead frame components while making the density of manufactured semiconductor devices higher. Additionally, a semiconductor device and a method for manufacturing is provided.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Dolores Milo
  • Publication number: 20240145354
    Abstract: A semiconductor device and method of manufacturing is provided, including a lead frame with a first and a second lead frame surface, a semiconductor die including a first and a second semiconductor die surface, a clip including a flat and a corrugated part, the corrugated part includes at least one peak and one valley, and a mold compound, the second lead frame surface is connected to the first die surface of the die, and the second die surface of the die is connected to the corrugated part, and the mold compound encapsulates the semiconductor die, and the valley of the corrugated part, so that the mold compound forms an outer surface of the device with the peak of the corrugated part, at least part of the flat part of the clip, and the first lead frame surface of the lead frame is exposed.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Arnel Taduran, Ricardo Yandoc, Homer Malveda, Antonio Dimaano
  • Publication number: 20240071780
    Abstract: An electronic package and method for manufacturing the same is provided. The method includes providing a frame with die pads, each pad having a semiconductor die that have a first electrical contact on a first side of the die facing and electrically contacting the pad, and a second electrical contact on a second side of the die opposite to the first side, providing a first conductive mechanical support connected to the pad and/or a second conductive mechanical support connected to the second electrical contact, and providing a mold including a first mold portion which the frame is on, and a second mold portion in contact with the frame opposite to the first mold portion, forming a cavity around the dies, the second mold portion contacts at least one of the first conductive mechanical support and the second conductive mechanical support, while applying the molding compound and allowing it to solidify.
    Type: Application
    Filed: August 28, 2023
    Publication date: February 29, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Matthew Anthony, Adam Brown
  • Publication number: 20230402351
    Abstract: According to the disclosure a semiconductor package assembly is proposed, at least including: a lead metallic frame; a semiconductor die structure being mounted on a die pad of the lead metallic frame; at least a first bond clip connected with the semiconductor die structure; at least a further bond clip connected with the die pad of the lead metallic frame via a solder junction; and the die pad is provided with at least one recess near the connection with the at least further bond clip for accommodating solder for the solder junction. The disclosure also pertains to a method for manufacturing such a semiconductor package assembly.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 14, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Matthew Anthony, Zhou Zhou, Adam Brown
  • Publication number: 20230326836
    Abstract: Aspects of the present disclosure relate to a semiconductor device package and to a method for manufacturing the same. The semiconductor device package includes a semiconductor die having a circuit integrated thereon, a first clip including a first planar portion and one or more first leads extending from the first planar portion, the first planar portion including one or more first protrusions, and a second clip including a second planar portion and one or more second leads extending from the second planar portion, the second planar portion including a plurality of second protrusions. The first planar portion and the second planar portion each physically and electrically connected to a terminal of the circuit arranged on the semiconductor die. At least one of the one or more first protrusions extends in a space between a pair of second protrusions among the plurality of second protrusions.
    Type: Application
    Filed: April 11, 2023
    Publication date: October 12, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Matthew Anthony, Jorex Lumanog
  • Patent number: 11728179
    Abstract: A surface mount semiconductor device and method of manufacture. A semiconductor die is mounted on a first support surface; a leadframe is attached to the semiconductor die, the leadframe comprising: an electrical lead having a first lead region connected to the semiconductor die; and a second lead region distal the first lead region, wherein the second lead region is connected to a second support surface; encapsulating the semiconductor die, first support surface and the first lead region; the second lead region is severed from the second support surface to expose a lead end; and the second lead region is electro-plated with a metallic material, such that the lead end is coated with said metallic material.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 15, 2023
    Assignee: Nexperia B.V.
    Inventors: Ricardo Yandoc, Adam Richard Brown, Haibo Fan, Kow Siew Ting, Nam Khong Then, Wei Leong Tan
  • Publication number: 20230223320
    Abstract: A semiconductor device package and a method for manufacturing the same is provided. The semiconductor device package includes a semiconductor die having an electronic component integrated thereon and having a die terminal that is electrically connected to the electronic component, a stress relief substrate fixedly and electrically connected to the die terminal, and a clip lead. The substrate is configured to provide an electrical short between the clip lead and the die terminal. The stress relief substrate may form an interface between the clip lead and the semiconductor die and can thereby reduce stress exerted on the semiconductor die by the clip lead.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 13, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Adam Brown, Zhou Zhou
  • Publication number: 20230154883
    Abstract: A semiconductor package including a semiconductor die having multiple bond pads is provided. The package further includes an electrically conducting clip including, at a first side thereof, at least one pin for mounting the package to an external board and includes, at a second side opposite to the first side, a connecting portion connecting the clip to at least two bond pads of the multiple bond pads. The connection portion includes at least two elongated connecting strips spaced apart from each other at a distance in such a manner that each strip extends over at least one of the at least two bond pads and is connected thereto.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 18, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Adam Brown, Haibo Fan
  • Publication number: 20230123782
    Abstract: A method of manufacturing a cascode HEMT semiconductor device including a lead frame, a die pad with an indentation attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Robert Montgomery, Adam Thomas Rosillo
  • Publication number: 20230028579
    Abstract: A semiconductor device is provided that includes a lead frame, a die attached to the lead frame using a first solder, a source clip and a gate clip attached to the die using a second solder, and a drain clip attached to the lead frame. The semiconductor device is inverted, so that the source clip and the gate clip are positioned on the bottom side of the semiconductor device, and the lead frame is positioned on the top side of the semiconductor device so that the lead frame is a top exposed drain clip.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 26, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Adam Brown, Qingyuan Tang
  • Publication number: 20230005846
    Abstract: A semiconductor device is provided, including a leadframe, a die attached to the leadframe using a first solder, a source clip and a gate clip attached to the die using a second solder, and a drain clip attached to the leadframe. The semiconductor device is inverted, so that the source clip and the gate clip are positioned on the bottom side of the semiconductor device, and the leadframe is positioned on the top side of the semiconductor device so that the leadframe is a top exposed drain clip. The source clip and/or the drain clip comprise a half cut locking feature. The half cut locking feature can be formed as a wing and located at the sides of the source clip and the gate clip.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 5, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Adam Brown, Norman Stapelberg, Manoj Balakrishnan
  • Patent number: 11538744
    Abstract: This disclosure relates to a cascode HEMT semiconductor device including a lead frame, a die pad attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: December 27, 2022
    Assignee: Nexperia B.V.
    Inventors: Ricardo Yandoc, Robert Montgomery, Adam Thomas Rosillo
  • Publication number: 20220293525
    Abstract: A lead-frame based packaged half-bridge circuit is provided that is useful in power electronics applications, such as DC-DC converters and motor controllers. The circuit reduces or eliminates unwanted additional resistance and inductance produced from interconnections that degrade performance in typical packaged half-bridge circuits.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 15, 2022
    Applicant: NEXPERIA B.V.
    Inventor: Ricardo Yandoc
  • Publication number: 20220262712
    Abstract: A semiconductor device is provided, including a MOSFET die, a first GaN die and a second GaN die. The first GaN die and the second GaN die are arranged in a cascode arrangement. The second GaN die is positioned in an inverted orientation. The MOSFET die controls the first GaN die and the second GaN die.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 18, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Dilder Chowdhury, Ilyas Dchar
  • Publication number: 20220230942
    Abstract: A packaged semiconductor device is provided, including a first semiconductor die on which a first electrical component is integrated that includes a first terminal at a first surface of the first die and a second terminal at a second surface of the first die, a second semiconductor die similar to the first die, with a first surface of the second die facing the first surface of the first die. A first conductive element on the second surface of the first side electrically connected to the second terminal of the first electrical component, a second conductive element is on the second surface of the second die electrically connected to the second terminal of the second electrical component, and a third conductive element between the first surfaces of the first and the second die. The first terminals of the first and second electrical components are electrically connected through the third conductive element.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 21, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo YANDOC, Adam BROWN, Phil RUTTER
  • Publication number: 20220139724
    Abstract: A semiconductor device including a clip, and the clip includes a clip slot, and a slug and the slug includes a groove. The clip and the slug are attached by the ultrasonic welding. The groove and the clip slot are at least partially overlapping to form a gas pathway.
    Type: Application
    Filed: November 4, 2021
    Publication date: May 5, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Anthony Matthew, Manoj Balakrishnan, Adam Brown
  • Publication number: 20210343627
    Abstract: A semiconductor device including a lead frame, a die attached to the lead frame using a first solder, and a clip attached to the die using a second solder is provided. The clip includes a notch arranged for a check of the excess of the second solder.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 4, 2021
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo YANDOC, Florante FENOL, Marlon FADULLO, Ramil ATIENZA
  • Publication number: 20210296218
    Abstract: This disclosure relates to a cascode HEMT semiconductor device including a lead frame, a die pad attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 23, 2021
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo YANDOC, Robert MONTGOMERY, Adam Thomas ROSILLO
  • Publication number: 20190067033
    Abstract: A surface mount semiconductor device and method of manufacture. A semiconductor die is mounted on a first support surface; a leadframe is attached to the semiconductor die, the leadframe comprising: an electrical lead having a first lead region connected to the semiconductor die; and a second lead region distal the first lead region, wherein the second lead region is connected to a second support surface; encapsulating the semiconductor die, first support surface and the first lead region; the second lead region is severed from the second support surface to expose a lead end; and the second lead region is electro-plated with a metallic material, such that the lead end is coated with said metallic material.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 28, 2019
    Inventors: Ricardo YANDOC, Adam Richard BROWN, Haibo FAN, Kow Siew TING, Nam Khong THEN, Wei Leong TAN