Abstract: An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body region and the drain region formed in the semiconductor material layer. The source and drain regions are spaced apart from each other by a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, the insulated gate extending over the charge carriers drift portion. The drain region is located at a depth compared to the front surface for causing charge carriers to move in the charge carriers drift portion away from an interface between the semiconductor material layer and the gate dielectric.

Abstract: A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract: A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer partially suspended above a semiconductor substrate and constrained to the substrate by temporary anchorages; dividing the layer into a plurality of portions laterally separated from one another; and removing the temporary anchorages, in order to free the portions.

Abstract: A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.

Abstract: An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body region and the drain region formed in the semiconductor material layer. The source and drain regions are spaced apart from each other by a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, the insulated gate extending over the charge carriers drift portion. The drain region is located at a depth compared to the front surface for causing charge carriers to move in the charge carriers drift portion away from an interface between the semiconductor material layer and the gate dielectric.

Abstract: An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a source region in the body region. A portion of the body region between drain and source regions forms a channel region. A polycrystalline silicon structure extends along the edge of the opening, partially on the field insulating and active layers. The polycrystalline silicon structure includes a gate region extending along a first portion of the edge on the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region.

Abstract: High-Q, variable capacitance capacitor is formed by including a pocket of semiconductor material; a field insulating layer, covering the pocket; an opening in the field insulating layer, delimiting a first active area; an access region formed in the active area and extending at a distance from a first edge of the active area and adjacent to a second edge of the active area. A portion of the pocket is positioned between the access region and the first edge and forms a first plate; an insulating region extends above the portion of said body, and a polysilicon region extends above the insulating region and forms a second plate. A portion of the polysilicon region extends above the field insulating layer, parallel to the access region; a plurality of contacts are formed at a mutual distance along the portion of the polysilicon region extending above the field insulating layer.

Abstract: An inductive structure integrated in a semiconductor substrate, comprising at least a conductive element insulated from the substrate, comprising an insulating structure, which is formed inside said semiconductor substrate and built close to said conductor element, so that the resistance of said substrate is increased and the parasitic currents induced by the conductor element in the substrate are decreased. The insulating structure including a plurality of insulating elements each surrounding a respective one of a plurality of semiconductor islands of the substrate.

Abstract: High-Q, variable capacitance capacitor is formed by including a pocket of semiconductor material; a field insulating layer, covering the pocket; an opening in the field insulating layer, delimiting a first active area; an access region formed in the active area and extending at a distance from a first edge of the active area and adjacent to a second edge of the active area. A portion of the pocket is positioned between the access region and the first edge and forms a first plate; an insulating region extends above the portion of said body, and a polysilicon region extends above the insulating region and forms a second plate. A portion of the polysilicon region extends above the field insulating layer, parallel to the access region; a plurality of contacts are formed at a mutual distance along the portion of the polysilicon region extending above the field insulating layer.

Abstract: An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a source region in the body region. A portion of the body region between drain and source regions forms a channel region. A polycrystalline silicon structure extends along the edge of the opening, partially on the field insulating and active layers. The polycrystalline silicon structure includes a gate region extending along a first portion of the edge on the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region.

Abstract: An inductive structure integrated in a semiconductor substrate, comprising at least a conductive element insulated from the substrate, comprising an insulating structure, which is formed inside said semiconductor substrate and built close to said conductor element, so that the resistance of said substrate is increased and the parasitic currents induced by the conductor element in the substrate are decreased. The insulating structure including a plurality of insulating elements each surrounding a respective one of a plurality of semiconductor islands of the substrate.

Abstract: A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and shaping the silicon oxide layer to form second delimiting walls inclined with respect to the substrate. The first walls have an angle of between approximately 70° and 110° with respect to the surface of the substrate; the second walls have an angle of between approximately 30° and 70° with respect to the surface of the substrate 11. The first delimiting walls are formed using a first mask and etching anisotropically first portions of the oxide layer; the second delimiting walls are formed using a second mask and carrying out a damage implantation for damaging second portions of the oxide layer and subsequently wet etching the damaged portions.

Abstract: The invention relates to an electronic level shifter circuit for driving a high-voltage output stage. This output stage comprises a complementary pair of transistors connected between first and second supply voltage references, and at least one PMOS pull-up transistor connected in series with an NMOS pull-down transistor. An additional transistor is connected in parallel with the pull-up transistor, and the driver circuit has a first output connected to the control terminal of the pull-up transistor and a second output connected to the control terminal of the additional transistor.

Abstract: A method, and related circuit, prevent the triggering of a parasitic transistor in an output stage of an electronic circuit. The stage includes a transistor pair with at least one transistor of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor having a terminal connected to the body terminal. The method includes the steps of providing a capacitor connected between the body and source terminals of the PMOS transistor; and using a control circuit to suppress the body effect of the pull-up PMOS transistor.

Abstract: The invention relates to a high-voltage final output stage for driving an electric load, of the type which comprises a complementary pair of transistors connected between first and second supply voltage references, and at least one PMOS pull-up transistor connected in series with an NMOS pull-down transistor. The stage comprises an additional PMOS transistor connected in parallel with the pull-up transistor and having the body terminal in common therewith. More particularly, the body terminals of both PMOS transistors are formed in the semiconductor within a common well which can withstand high voltages, and the additional transistor is a thick oxide PMOS power transistor.

Abstract: The DMOS transistor includes an n drain region, a p body region which forms, with the drain region, a junction having at least one edge portion with a small radius of curvature, an n+ source region which delimits a channel in the body region, p+ body contact regions, a gate electrode, a source and body electrode, and a drain electrode. To prevent the "snap-back" phenomenon when the junction is reverse biased with the source, body and gate electrodes short-circuited, a p+ region is associated with each of the edge portions having a small radius of curvature and is arranged so as to be closer to the associated edge portion than any part of the source region.

Abstract: The invention relates to a structure for and the method of manufacturing a driver circuit for an inductive load monolithically integrated on a semiconductor substrate doped with a first type of doping agent and on which is grown an epitaxial well having a second type of doping agent. An insulated well doped with the same type of doping agent as the substrate, which houses at least one power transistor of the driver circuit, is provided within the epitaxial well. The epitaxial well also houses a first and a second active area which house the cathode terminal and anode terminal of a protection diode, respectively.

Abstract: N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and the doping level of a well region. The devices may be configured as source or drain followers without problems.

Abstract: An integrated device including a structure for protection against electric fields. The protection structure may include a first region of conducting material electrically connected to the gate/source region of the device at a first potential. The protection structure may also include a second region of conducting material electrically connected to the drain region of the device at a second potential differing from the first. In one embodiment, the first region of conducting material is comb-shaped, and includes a first number of fingers separated by a plurality of gaps. The second region of conducting material includes portions extending at the aforementioned gaps to form a comb structure. Thus, the body of semiconductor material of the device sees a protection region formed by a pair of interlocking comb structures at an intermediate potential between the first and second potentials.

Abstract: A method is disclosed for forming a first region with conductivity of a first type and second, buried region with conductivity of a second type which forms a junction with the first region. By first and second doping steps, impurities of a first and a second type are successively introduced into a silicon chip. A high-temperature treatment causes the impurities thus introduced to diffuse and form said first and second regions. In order to provide a buried region whose concentration and/or depth are little dependent on process parameters, the second doping step comprises a first sub-step of low dosage and high energy implantation, and a second sub-step of low dosage and high energy implantation. The dosages and energies are such that they will not compensate or reverse the type of conductivity of the first region, and such that the concentration in the second region will be substantially due to the second implantation step only.