Patents by Inventor Riccardo Locatelli
Riccardo Locatelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10846439Abstract: A system to evaluate functional safety in an integrated circuit. The system includes a first circuit to execute an operation to cause to system to perform a function, where the function associated with a specified safety integrity level. The system also includes second circuit to capture trace data at an interface to the first circuit or at internal signals without inhibiting performance of the function, where the trace data comprising information that is used to determine whether the system can perform the function with an indicated level of functional safety and transmit the trace data to a safety evaluation circuit.Type: GrantFiled: June 28, 2019Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Riccardo Locatelli, Peter Lachner, Riccardo Mariani, Michael Paulitsch, Kevin Safford
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Patent number: 10540277Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.Type: GrantFiled: October 15, 2014Date of Patent: January 21, 2020Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Giuseppe Maruccia, Giuseppe Guarnaccia, Raffaele Guarrasi
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Publication number: 20190370503Abstract: A system to evaluate functional safety in an integrated circuit. The system includes a first circuit to execute an operation to cause to system to perform a function, where the function associated with a specified safety integrity level. The system also includes second circuit to capture trace data at an interface to the first circuit or at internal signals without inhibiting performance of the function, where the trace data comprising information that is used to determine whether the system can perform the function with an indicated level of functional safety and transmit the trace data to a safety evaluation circuit.Type: ApplicationFiled: June 28, 2019Publication date: December 5, 2019Inventors: Riccardo Locatelli, Peter Lachner, Riccardo Mariani, Michael Paulitsch, Kevin Safford
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Patent number: 10419432Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.Type: GrantFiled: October 17, 2014Date of Patent: September 17, 2019Assignees: STMicroelectronics SA, STMicroelectronics (Grenoble2) SAS, STMicroelectronics S.R.L.Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Hajer Ferjani, Giuseppe Maruccia, Raffaele Guarrasi, Giuseppe Guarnaccia
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Patent number: 9660936Abstract: A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.Type: GrantFiled: October 16, 2014Date of Patent: May 23, 2017Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.Inventors: Riccardo Locatelli, Michael Soulie, Francesco Giotta, Raffaele Guarrasi, Giuseppe Guarnaccia
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Patent number: 9461913Abstract: Embodiments relate to a method for transmitting a message in a data path of a network, the method includes transmitting a message onto an input bus of an input interface module, the message being received in flits of a size corresponding to the width of the input bus and generating a validity indicator for each elementary flit constituting each flit received. The message is transmitted onto an output bus of the input interface module towards a receiving interface module in flits of a size corresponding to the width of the output bus along with each validity indicator generated in association with the corresponding elementary flit. The receiving interface module receives flits constituting the message and the associated validity indicators and rejects a received flit if an elementary flit of the received flit is associated with a validity indicator in the invalid state.Type: GrantFiled: May 14, 2013Date of Patent: October 4, 2016Assignee: STMicroelectronics (Grenoble 2) SASInventors: Michael Soulie, Riccardo Locatelli, Antonio-Marcello Coppola
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Publication number: 20160246714Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.Type: ApplicationFiled: October 15, 2014Publication date: August 25, 2016Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Giuseppe Maruccia, Giuseppe Guarnaccia, Raffaele Guarrasi
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Publication number: 20160226878Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.Type: ApplicationFiled: October 17, 2014Publication date: August 4, 2016Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Hajer Ferjani, Giuseppe Maruccia, Raffaele Guarrasi, Giuseppe Guarnaccia
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Patent number: 9306844Abstract: A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.Type: GrantFiled: November 9, 2012Date of Patent: April 5, 2016Assignee: STMicroelectronics (Grenoble 2) SASInventors: Riccardo Locatelli, Esa Petri, Antonio-Marcello Coppolla, Luca Fanucci, Sergio Saponara, Tony Bacchillone
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Publication number: 20150109916Abstract: A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.Type: ApplicationFiled: October 16, 2014Publication date: April 23, 2015Inventors: Riccardo Locatelli, Michael Soulie, Francesco Giotta, Raffaele Guarrasi, Giuseppe Guarnaccia
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Patent number: 8825986Abstract: A switch includes at least one input configured to receive data and at least two outputs configured to send data to at least two further switches in a network via at least two output links. Each output link has a known hop value. The switch further includes a direction determinator that determines a routing direction for the data from information identifying a relative location of the switch in the network and information identifying a destination of said data. A distributor within the switch processes the routing direction and direction information about each output link in order to select one of said at least two outputs for outputting said data. The selection that is made prioritizes output links for selection which have relatively higher known hop values.Type: GrantFiled: October 13, 2011Date of Patent: September 2, 2014Assignee: STMicroelectronics (Grenoble 2) SASInventors: Antonio-Marcello Coppola, Riccardo Locatelli, Jose Flich Cardo, Jose Cano Reyes, Jose Francisco Duato Marin
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Publication number: 20140050221Abstract: An interconnect arrangement includes a plurality of tag allocators. Each tag allocator is configured to receive at least one stream of a plurality of packet units and further configured to tag each packet unit. Each packet unit is tagged with one of a set of n tags where n is greater than two. At least one stream is tagged with a sequence of tags that is different from a sequence of tags used for at least one other of said streams. The interconnect arrangement also includes a router configured to receive a plurality of streams of tagged packet units and to arbitrate between the streams such that packet units having a same tag are output in a group.Type: ApplicationFiled: August 16, 2012Publication date: February 20, 2014Applicants: STMicroelectronics, Inc., STMicroelectronics (Grenoble 2) SASInventors: Riccardo Locatelli, Rene Peyard, Michael Bekerman
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Publication number: 20130301643Abstract: Embodiments relate to a method for transmitting a message in a data path of a network, the method includes transmitting a message onto an input bus of an input interface module, the message being received in flits of a size corresponding to the width of the input bus and generating a validity indicator for each elementary flit constituting each flit received. The message is transmitted onto an output bus of the input interface module towards a receiving interface module in flits of a size corresponding to the width of the output bus along with each validity indicator generated in association with the corresponding elementary flit. The receiving interface module receives flits constituting the message and the associated validity indicators and rejects a received flit if an elementary flit of the received flit is associated with a validity indicator in the invalid state.Type: ApplicationFiled: May 14, 2013Publication date: November 14, 2013Inventors: Michael Soulie, Riccardo Locatelli, Antonio-Marcello Coppola
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Patent number: 8352628Abstract: A method is for transferring data from a source target to a destination target in a network. The method includes sending at least one request packet for the destination target, with the request packet containing information relating to a first address where data are located and a second address where data are to be stored. Moreover, at least one transaction request is sent to the source target, with the read request being elaborated from information contained in the request packet. The source target transfers the data located at the first address to the second address.Type: GrantFiled: June 20, 2008Date of Patent: January 8, 2013Assignee: STMicroelectronics SAInventors: Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Marcello Coppola
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Publication number: 20120134364Abstract: A switch includes at least one input configured to receive data and at least two outputs configured to send data to at least two further switches in a network via at least two output links. Each output link has a known hop value. The switch further includes a direction determinator that determines a routing direction for the data from information identifying a relative location of the switch in the network and information identifying a destination of said data. A distributor within the switch processes the routing direction and direction information about each output link in order to select one of said at least two outputs for outputting said data. The selection that is made prioritizes output links for selection which have relatively higher known hop values.Type: ApplicationFiled: October 13, 2011Publication date: May 31, 2012Inventors: Antonio-Marcello Coppola, Riccardo Locatelli, Jose Flich Cardo, Jose Cano Reyes, Jose Francisco Duato Marin
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Patent number: 8185934Abstract: A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.Type: GrantFiled: September 9, 2008Date of Patent: May 22, 2012Assignee: STMicroelectronics (Grenoble) SASInventors: Valerio Catalano, Marcello Coppola, Riccardo Locatelli, Cristina Silvano, Gianluca Palermo, Leandro Fiorin
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Patent number: 8165120Abstract: This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: retrieving from the first device request packets comprising request control data for controlling data transfer and actual request data to be transferred; storing said request control and data to be transferred in memory means provided in an network interface (NI); and elaborating data packets to be transferred to the second device through said network, said data packets comprising a header and a payload elaborated from said control data and said actual data, respectively; The control data and the actual data to be transferred are stored in separate first and second memory means.Type: GrantFiled: November 10, 2008Date of Patent: April 24, 2012Assignee: STMicroelectronics (Grenoble) SASInventors: Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Marcello Coppola
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Patent number: 7940788Abstract: A system is for transmitting data in a network and includes emitter nodes, each including a transmitter for transmitting requests for data transmission. The system may also include a receiver node receiving the data transmission from the emitter nodes and including a first memory for storing data transmitted by each emitter node, a second memory for storing the requests, and a transmitter. The data may be transmitted from the emitter nodes to the receiver node when memory space is available in the first memory to receive data. The transmitter of the receiver node may transmit to each emitter node an acknowledgement message when memory space is available in the first memory to receive at least a portion of the data transmitted. Each emitter node may establish a communication link with the receiver node and transmits the data based upon the acknowledgement message. The communication link may be locked until all data is transmitted.Type: GrantFiled: January 28, 2008Date of Patent: May 10, 2011Assignee: STMicroelectronics SAInventors: Michael Soulie, Riccardo Locatelli, Marcello Coppola
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Patent number: 7861018Abstract: A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.Type: GrantFiled: December 18, 2007Date of Patent: December 28, 2010Assignee: STMicroelectronics SAInventors: Philippe Teninge, Riccardo Locatelli, Marcello Coppola, Lorenzo Pieralisi, Giuseppe Maruccia
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Patent number: D673207Type: GrantFiled: December 2, 2009Date of Patent: December 25, 2012Assignee: Roland CorporationInventors: Fumihiko Miura, Ena Ito, Riccardo Locatelli