Abstract: A method for executing programs (P) in an electronic system for applications provided with functional safety that includes a single-processor or multiprocessor processing system and a further independent control module, the method comprising: performing an operation of breaking-down of a program (P) into a plurality of parallel sub-programs (P1, . . . , Pn); assigning execution of each parallel sub-program (P1, . . . , Pn) to a respective processing module of the system, periodically performing self-test operations (Astl, Asys, Achk) associated to each of said sub-programs (P1, . . .

Abstract: A method for simulating faults in integrated circuits of electronic systems implementing applications under functional safety includes operating a simulation step of the system or electronic circuit on a processing system and executing the application under functional safety. The simulation step has a fault injection procedure including injecting a set of faults during simulation in determined locations, and verifying if observation points and diagnostic points connected to determined root failure modes are perturbed. The simulation step includes before the injecting step during simulation in determined locations of an electronic circuit performing a procedure to select a set of effective faults, pertaining only to effective root failure modes, which allow obtainment of the overall diagnostic coverage target, and supplying the set of effective faults for the execution of the injecting step during simulation in determined locations of the electronic circuit.

Abstract: A method for measuring the effect of microscopic hardware faults in high-complexity applications includes carrying out on a processing system a step of simulation of an electronic system that executes a software instance of the application. The simulation step includes injecting faults at a microscopic level and measuring a corresponding final effect. The operation of injecting faults includes selecting a microscopic fault to be injected, selecting a mutant corresponding to the microscopic fault, applying the selected mutant to the software instance to obtain a mutated instance, simulating the electronic system that executes the mutated instance, and measuring the corresponding effect.

Abstract: A tool for performing a functional safety analysis of an integrated circuit device tailored to a customer's specific application and implementation of the device. Information regarding a user's specific implementation of a given integrated circuit device is provided by the customer as input to the safety analysis tool. The tool then automatedly performs a functional safety analysis based on the information regarding the user's specific implementation of the integrated circuit device. In one embodiment, the customer specifies specific functional modules of the integrated circuit device, and the tool performs a functional safety analysis of the integrated circuit device that considers the functional modules selected by the user.

Abstract: A method for performing failure mode and effects analysis (FMEA) on integrated circuits including preparing a FMEA database of an integrated circuit under design and computing FMEA results from the FMEA database. Information is automatically extracted from an integrated circuit description. The extraction of information includes reading integrated circuit information, partitioning the circuit in invariant and elementary sensitive zones (SZ), using the information in the preparation step of a FMEA database. Optionally a FMEA validation stage may be performed with which FMEA computed results are compared with FMEA measured results to obtain FMEA validated results.

Abstract: A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault processing unit is external and different with respect to said central processing unit and said further fault processing unit comprises at least a module for performing validation of operations of said central processing unit and one or more modules suitable for performing validation of operations of other functional parts of said microcontroller. Validation of operations of said central processing unit is performed by using one or more of the following fault tolerance techniques: data shadowing; code&flow signature; data processing legality check; addressing legality check; ALU concurrent integrity checking; concurrent mode/interrupt check.

Abstract: A method for performing failure mode and effects analysis (FMEA) on integrated circuits including preparing a FMEA database of an integrated circuit under design and computing FMEA results from the FMEA database. Information is automatically extracted from an integrated circuit description. The extraction of information includes reading integrated circuit information, partitioning the circuit in invariant and elementary sensitive zones (SZ), using the information in the preparation step of a FMEA database. Optionally a FMEA validation stage may be performed with which FMEA computed results are compared with FMEA measured results to obtain FMEA validated results.

Abstract: A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault processing unit is external and different with respect to said central processing unit and said further fault processing unit comprises at least a module for performing validation of operations of said central processing unit and one or more modules suitable for performing validation of operations of other functional parts of said microcontroller. Validation of operations of said central processing unit is performed by using one or more of the following fault tolerance techniques: data shadowing; code&flow signature; data processing legality check; addressing legality check; ALU concurrent integrity checking; concurrent mode/interrupt check.