Abstract: In one embodiment, network devices such as IP phones may be upgraded with a set of files. A master network device in the set of network devices is identified. The master network device retrieves or receives one or more files in the set of files. The master network device then distributes the file(s) to one or more network devices in the set of network devices, thereby enabling the file(s) to be distributed in a hierarchical manner to remaining network devices in the set of network devices.

Abstract: In one embodiment, network devices such as IP phones may be upgraded with a set of files. A master network device in the set of network devices is identified. The master network device retrieves or receives one or more files in the set of files. The master network device then distributes the file(s) to one or more network devices in the set of network devices, thereby enabling the file(s) to be distributed in a hierarchical manner to remaining network devices in the set of network devices.

Abstract: In one embodiment, network devices such as IP phones may be upgraded with a set of files. A master network device in the set of network devices is identified. The master network device retrieves or receives one or more files in the set of files. The master network device then distributes the file(s) to one or more network devices in the set of network devices, thereby enabling the file(s) to be distributed in a hierarchical manner to remaining network devices in the set of network devices.

Abstract: Various nanoscale logic gates are disclosed. An alternating current (“AC”) source is superimposed on a direct-current (“DC”), largely resistor-based nanoscale logic circuit in order to provide distinguishable, AC current or voltage logical output signals despite potentially narrow DC-voltage or DC-current ranges produced by the resistor-based nanoscale logic circuit. AC-enhanced AND, OR, NAND, and NOR nanoscale logic gates are provided as four specific embodiments of the present invention.

Abstract: Various nanoscale logic gates are disclosed. An alternating current (“AC”) source is superimposed on a direct-current (“DC”), largely resistor-based nanoscale logic circuit in order to provide distinguishable, AC current or voltage logical output signals despite potentially narrow DC-voltage or DC-current ranges produced by the resistor-based nanoscale logic circuit. AC-enhanced AND, OR, NAND, and NOR nanoscale logic gates are provided as four specific embodiments of the present invention.

Abstract: A signal processing channel and method for reducing intersymbol interference in a sequence of data symbols includes a pre-shaping filter for sharpening leading edges of data symbols and providing trailing edges that approximate a decaying exponential. The output of the pre-shaping filter is combined with a cancellation output from a resistance-capacitance circuit having a time constant selected to provide pulse responses that complement the exponentially decaying trailing edges. The combination of the shaped output and the cancellation output is input to a slicer or other decision device. The 2-level output from the slicer is an input to a decision feedback filter that generates the cancellation output. In addition to the resistance-capacitance circuit, the decision feedback filter includes a delay to properly time the coincidence of the cancellation output with the shaped output from the pre-shaping filter.

Abstract: An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.

Abstract: Signal processing system for reducing error due to intersymbol interference and other noise, the system having a feedforward equalizer adaptively responsive to a first error signal (e.sub.n) and having a noise decorrelator adaptively responsive to an adjusting signal (q.sub.n) derived from the first error signal. In a preferred embodiment the source of the signal (S.sub.n) is a magnetic disk having encoded data thereon. The feedforward equalizer reduces intersymbol interference. A decision device connected to the feedforward equalizer is coupled to connect the signal (X.sub.n) from the feedforward equalizer into a stream (d.sub.n) of data samples having a limited number of predetermined signal levels. The first error signal is the difference between signal levels of data samples in the stream and the output of the feedforward equalizer. The first error signal is utilized to adjust the feedforward equalizer and to provide an input to the noise decorrelator.

Abstract: Magnetic recording and reading apparatus and a method in which two modes of operation, read-after-write and read-only, for setting read signal amplitude qualification threshold are provided. In the read-after-write mode, a fixed amplitude qualification threshold is utilized, typically being fifty percent of the peak amplitude of a perfect dropout-free read signal. The read-only mode amplitude qualification threshold is derived from the average peak rectified read signal, and varies with it. The threshold is selected to provide that fraction of the average peak rectified read signal which gives the lowest acceptable dropout or error rate.

Abstract: A differential detection device is provided for detecting the presence of magnetic bubbles in a data stream circulating on a magnetic wafer. The device utilizes an array of columns of permalloy elements to enlarge the magnetic bubbles being detected. A change in resistance of each of a pair of adjacent permalloy columns as a bubble traverses the detector is sensed and differentially detected to signify the presence of the bubble. In one embodiment of the invention, a second detector is used in conjunction with the first detector to provide operation in a mode in which bubbles in alternate positions in the data stream are directed into alternate channels including the first and second detectors respectively. After detection, the bubbles are redirected into a single data stream, while the output signals from the two detectors are merged to produce a data output signal reproducing the original data stream.