Patents by Inventor Richard A. Carberry

Richard A. Carberry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10492275
    Abstract: A system and method provide fail-safe operation of a lighting system. A lighting level detector is used to obtain a baseline lighting level for a low-intensity light. If the detector measures less than the baseline level when an occupancy sensor determines the space is unoccupied, a high-intensity light is energized and an indication is provided to a user that the low-intensity light has failed. A method provides daylighting operation of a lighting system. An occupancy sensor can have Wi-Fi functionality to enable remote configuration of the sensor. A line voltage occupancy sensor can include an interface with low voltage devices. An occupancy sensor can include an integral interface to enable an external control system to override the sensor's normal logic under emergency conditions. An occupancy sensor can include an active temperature compensation feature. An occupancy sensor can also incorporate an automatically adjustable coverage area.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: November 26, 2019
    Assignee: Leviton Manufacturing Co., Inc.
    Inventors: Richard A. Leinen, Brian Carberry, David Buerer, Jaiganesh Balasubramanian
  • Publication number: 20190239313
    Abstract: A system and method provide fail-safe operation of a lighting system. A lighting level detector is used to obtain a baseline lighting level for a low-intensity light. If the detector measures less than the baseline level when an occupancy sensor determines the space is unoccupied, a high-intensity light is energized and an indication is provided to a user that the low-intensity light has failed. A method provides daylighting operation of a lighting system. An occupancy sensor can have Wi-Fi functionality to enable remote configuration of the sensor. A line voltage occupancy sensor can include an interface with low voltage devices. An occupancy sensor can include an integral interface to enable an external control system to override the sensor's normal logic under emergency conditions. An occupancy sensor can include an active temperature compensation feature. An occupancy sensor can also incorporate an automatically adjustable coverage area.
    Type: Application
    Filed: April 4, 2019
    Publication date: August 1, 2019
    Inventors: Richard A. Leinen, Brian Carberry, David Buerer, Jaiganesh Balasubramanian
  • Patent number: 7317773
    Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: January 8, 2008
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
  • Publication number: 20040239365
    Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
    Type: Application
    Filed: July 9, 2004
    Publication date: December 2, 2004
    Applicant: Xilinx, Inc.
    Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
  • Patent number: 6777980
    Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: August 17, 2004
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
  • Patent number: 6621296
    Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: September 16, 2003
    Assignee: Xilinx, Inc.
    Inventors: Richard A. Carberry, Steven P. Young, Trevor J. Bauer
  • Publication number: 20030112032
    Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
    Type: Application
    Filed: January 15, 2003
    Publication date: June 19, 2003
    Applicant: Xilinx, Inc.
    Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
  • Publication number: 20030071653
    Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.
    Type: Application
    Filed: November 15, 2002
    Publication date: April 17, 2003
    Applicant: Xilinx, Inc.
    Inventors: Richard A. Carberry, Barbara Dahl, Steven P. Young, Trevor J. Bauer
  • Patent number: 6529040
    Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: March 4, 2003
    Assignee: Xilinx, Inc.
    Inventors: Richard A. Carberry, Steven P. Young, Trevor J. Bauer
  • Patent number: 6525565
    Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: February 25, 2003
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
  • Patent number: 6501296
    Abstract: A memory array having a read mode and a write mode is addressed using separate read and write decoders. The write decoder is used to write bit values to one column of the array. A hard-wired read decoder is utilized to further increase the operating speed during the memory read mode. In one embodiment, a separate read bit line is provided to facilitate faster read operations. In an exemplary embodiment, the write decoder receives two input signals and generates four write address signals on write word lines that are transmitted to the columns of programmable elements of a logic/memory array. The hard-wired read decoder also receives the same two input signals, and generates eight read address signals on two read word lines, two read address signals being transmitted to each column of the logic/memory array.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: December 31, 2002
    Assignee: Xilinx, Inc.
    Inventors: Ralph D. Wittig, Sundararajarao Mohan, Richard A. Carberry
  • Publication number: 20020175704
    Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
    Type: Application
    Filed: January 12, 2001
    Publication date: November 28, 2002
    Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
  • Patent number: 6480954
    Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: November 12, 2002
    Assignee: Xilinx Inc.
    Inventors: Stephen M. Trimberger, Richard A. Carberry, Robert Anders Johnson, Jennifer Wong
  • Patent number: 6445209
    Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The write decoder includes NOR gates that generate select signals used to address individual memory circuits during write operations. For dynamic latching during reading or shifting, each memory circuit includes an inverter circuit connected between the memory cell and the output terminal of the memory circuit. The read decoder includes a multiplexing circuit made up of a series of 2-to-1 multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: September 3, 2002
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Trevor J. Bauer, Richard A. Carberry
  • Patent number: 6373279
    Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). Each memory circuit includes an inverter circuit connected between the memory cell and the output terminal of the memory circuit. The write decoder includes NOR gates that generate select signals used to address individual memory circuits during write operations. The read decoder includes a multiplexing circuit made up of a series of 2-to-1 multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: April 16, 2002
    Assignee: Xilinx, Inc.
    Inventors: Trevor J. Bauer, Steven P. Young, Richard A. Carberry
  • Publication number: 20020010853
    Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.
    Type: Application
    Filed: June 6, 2001
    Publication date: January 24, 2002
    Applicant: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Richard A. Carberry, Robert Anders Johnson, Jennifer Wong
  • Publication number: 20010043082
    Abstract: A memory array having a read mode and a write mode is addressed using separate read and write decoders. The write decoder is used to write bit values to one column of the array. A hard-wired read decoder is utilized to further increase the operating speed during the memory read mode. In one embodiment, a separate read bit line is provided to facilitate faster read operations. In an exemplary embodiment, the write decoder receives two input signals and generates four write address signals on write word lines that are transmitted to the columns of programmable elements of a logic/memory array. The hard-wired read decoder also receives the same two input signals, and generates eight read address signals on two read word lines, two read address signals being transmitted to each column of the logic/memory array.
    Type: Application
    Filed: July 24, 2001
    Publication date: November 22, 2001
    Applicant: Xilink, Inc.
    Inventors: Ralph D. Wittig, Sundararajarao Mohan, Richard A. Carberry
  • Patent number: 6292019
    Abstract: A programmable logic device (PLD) includes at least one function generator capable of implementing any arbitrarily defined Boolean function of input signals. The PLD includes a dynamically controlled multiplexer (MUX) on each function-generator input terminal. The inputs of each MUX can be routed to the corresponding function-generator input terminal by providing an appropriate select signal on one or more control lines. One embodiment of the PLD includes a programmable look-up table (LUT) that permits routing software to determine the correspondence between the MUX input terminals and a user-defined selection code on the MUX select lines. In one embodiment, the correspondence between the NUX input terminals and the selection code is established by configuring a number of programmable memory cells in the LUT. Another embodiment enhances programming flexibility with an additional MUX connected between the control lines and the LUT.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: September 18, 2001
    Assignee: Xilinx Inc.
    Inventors: Bernard J. New, Richard A. Carberry
  • Patent number: 6288569
    Abstract: A memory array having a read mode and a write mode is addressed using separate read and write decoders. The write decoder is used to write bit values to one column of the array. A hard-wired read decoder is utilized to further increase the operating speed during the memory read mode. In one embodiment, a separate read bit line is provided to facilitate faster read operations. In an exemplary embodiment, the write decoder receives two input signals and generates four write address signals on write word lines that are transmitted to the columns of programmable elements of a logic/memory array. The hard-wired read decoder also receives the same two input signals, and generates eight read address signals on two read word lines, two read address signals being transmitted to each column of the logic/memory array.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: September 11, 2001
    Assignee: Xilinx, Inc.
    Inventors: Ralph D. Wittig, Sundararajarao Mohan, Richard A. Carberry
  • Patent number: 6263430
    Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: July 17, 2001
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Richard A. Carberry, Robert Anders Johnson, Jennifer Wong