Abstract: CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors before the gate terminals of each input switching transistor. Each shielding transistor has a gate terminal coupled to a shield voltage of a magnitude substantially midway between ground potential and the positive power supply voltage. The input signal is conveyed by the source-drain channel of the input shielding transistor to the gate of the switching transistor, while preventing the gate of the switching transistor from rising above the shield voltage, in the case of n-channel devices, or below the shield voltage, in the case of p-channel devices.

Abstract: A track and hold signal processing system is capable of driving 256 gray scale active matrix LCD displays at speeds limited only by the electrical characteristics of the display. The quiescent power dissipated by the system is substantially less than known track and hold drivers due to separation of the tracking circuit from the hold circuit resulting in optimization of the tracking function.

Abstract: A system and method minimizing switching errors in voltages delivered to a resistive load. Switch impedances can be significant when small resistor values are utilized. A system relies on varying the resistance in the switches to compensate for the output voltage errors. The selection of a particular CMOS input transmission gate depends upon which outputs of a resistor divider are selected. In concept, a system is created which replaces each input transmission gate with a resistor and a zero impedance switch. The combination of properly selected CMOS input transmission gates results in output offset voltage errors which are greatly reduced due to the matching impedances of the individual switches.

Abstract: A compensation circuit equalizes processing (speed) differences between driver chips used to drive an active matrix LCD display by inserting a delay in opposite proportion to the speed of the driver IC so that a faster IC will receive a longer delay and a slower IC will receive a shorter delay.

Abstract: A selective call receiver (200) includes a receiver (204) receiving paging signals including a preamble, a synchronization codeword, and at least address information. A controller (206) controlling a supply of power to the receiver for receiving the paging signals. A synchronization obtaining circuitry (404, 406, 224), coupled to the receiver (204), obtains synchronization to the paging signal. The synchronization obtaining circuitry (404, 406, 224) includes a baud rate detector and synchronization codeword detector, coupled to the baud rate detector, detects the synchronization codeword. An address decoder, responsive to the synchronization codeword being detected, decodes the address information. A synchronization maintaining circuitry (404, 408, 224) maintains synchronization to the paging signals during address decoding. The synchronization maintaining circuitry (404, 408, 224) includes circuitry for enabling the power switch (210) which enables the receiver (204) for receiving the paging signals.

Abstract: A radio receiver (100) having a receiver section (103) receives and processes an information signal to provide received information having an error factor that varies at least with respect to operational parameters of the receiver section (103). In the radio receiver (100), a method is embodied for adaptively controlling the operational parameters of the receiver section (103) to optimize the error factor of the received information. The method (400, 400', 400") comprises operating in a first receiver mode in response to a predetermined mode select parameter, correlating a first signal recovered from the received information to at least a portion of a first code word to establish a first error criteria, and operating in the first receiver mode while the first error criteria does not exceed a predetermined error criteria.

Abstract: A data recovery device (208) for recovering data symbols having a period T from a received data stream. The data recovery device samples at least one data symbol in the received data stream at a rate determined by an integration envelope (301) having the period T. The samples are accumulated as a weighted sample count representing a recovered data symbol that is then stored as at least one recovered data bit.

Abstract: A receiver (200) receives (203) a transmitted signal having a first predetermined signal for indicating a start of a new transmission to the receiver and having a second predetermined signal inserted at periodic sampling time intervals for synchronizing the receiver to the transmitted signal. The receiver (200) synchronizes to the transmitted signal by detecting the first predetermined signal (208) followed by the second predetermined signal (210), and establishing subsequent periodic sampling time intervals therefrom. The receiver (200) conserves power (228) during a second portion of a periodic sampling time interval following a detection of a first portion of the second predetermined signal (210) during a first portion of the periodic sampling time interval.

Abstract: A symbol synchronizer for a communication receiver receiving multi-level data signals includes a reference clock generator for generating a reference clock signal having a predetermined time period, a state change detector for detecting state changes occurring within the received multi-level data signals over the predetermined time period to enable determining a time location corresponding to the detected state change wherein the time locations are assigned predetermined numeric values corresponding to the time locations determined, an accumulator for accumulating a time location for the time locations selected, and a phase adjusting circuit which is responsive to the time location count for adjusting the phase of the reference clock signal relative to the received multi-level data signal.

Abstract: An apparatus and method for processing a signal is capable of determining the presence of absence of a signal having a predetermined baud rate. By initializing counting registers to either first or second values, and receiving the signal, either the presence or absence of the baud rate may be more rapidly detected. Rapid detection provides for improved battery savings when the invention is used within a portable receiver such as a pager. The invention provides for positive detection of the predetermined baud rate while rejecting a baud rate being an integer divisor of the predetermined baud rate. Additionally, as a result of the determination of the presence of the predetermined baud rate, a sample clock may be established for receiving data at the baud rate.

Abstract: An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked.

Abstract: An apparatus for determining if a received binary word corresponds to the true or complement version of a stored binary word includes means for serially multiplexing the bits of each binary word to the inputs of an exclusive OR gate. The exclusive-OR gate generates a logical high signal each time a mismatch occurs. These signals are applied directly to an error counter and, after inversion, to a match counter. The contents of the error counter and match counter are compared to a stored threshold number. A first signal is generated if the contents of the error counter exceeds the threshold. A second signal is generated if the contents of the match counter exceeds the threshold. Upon the occurrence of both signals, the serial comparison process is terminated.

Abstract: An apparatus and method for processing a signal is capable of determining the presence or absence of a signal having a predetermined baud rate. By initializing counting registers to either first or second values, and receiving the signal, either the presence or absence of the baud rate may be more rapidly detected. Rapid detection provides for improved battery savings when the invention is used within a portable receiver such as a pager. The invention provides for positive detection of the predetermined baud rate while rejecting a baud rate being an integer divisor of the predetermined baud rate. Additionally, as a result of the determination of the presence of the predetermined baud rate, a sample clock may be established for receiving data at the baud rate.

Abstract: A reconfigurable deinterleaver for deinterleaving up to N interleaved codewords, each up to M bits in length comprises a memory array, a memory for storing predetermined deinterleaver parameters, a controller, and column and row selector means. The memory array is configured with N bit rows by M bit columns, and is capable of selectably deinterleaving interleaved codewords. The predetermined deinterleaver parameters define the number and length of the interleaved codewords to be deinterleaved. The controller is responsive to the deinterleaver parameters for controlling the writing of interleaved codewords into the memory array and for reading deinterleaved codewords from the memory array. Column and row selector means provide for writing interleaved codewords into, and reading deinterleaved codewords from only a portion of the memory array when smaller data blocks are deinterleaved.

Abstract: A paging receiver receiving message information having one of a plurality of (BCH) code word structures has a programmable error correcting apparatus for correcting bit errors within the message information. The programmable error correcting apparatus may be configured in response to identifying a signalling system and the code word structure corresponding to ther signalling system, or in response to changes in the code word structure within the message. A simplified error correcting apparatus may correct a single bit error within a code word structure. The programamble error correcting apparatus is capable of correcting any two bit error combination within the code word structure and contains sequential and combinational logic circuits. The programmable error correcting apparatus is integrated together with a microprocessor on a monolithic integrated circuit.

Abstract: A baud rate detector determines the baud rates of signals received by a selective call receiver. If the signals have no detectable baud rate or the baud rate of the received signals does not match that of a plurality of known selective call network transmission baud rates, the selective call receiver indicates to its user that it is out of range of the network's transmitters.

Abstract: A mechanism for recovering respective binary states of an input data signal in synchronism with transitions of the input data signal carries out the following sequence of steps. First, the binary state of the input data signal is sampled in accordance with consecutively occurring transitions of a high speed clock signal, the repetition frequency of which is at least three times the data transition rate. Upon the occurrence of a difference in binary state of successive samples of the input data signal at consecutive transitions of the clock signal, a signal representative of such a change is generated. In response to this change of state or transition-representative signal, the binary state of a delayed version of the input data signal, at a time whereat the input data signal is stable, is sampled. In order to reliably monitor the state of the communication link over which the data is transmitted, the binary state of the input data signal is periodically sampled.