Abstract: An emitter ID ambiguity reduction system includes a Mission Data File Ambiguity Resolution matrix that contains both a) the INTEL-based emitter parameters data necessary to break emitter-by-emitter ambiguities, and b) the action(s) the Electronic Warfare (EW) system is to take to collect that data. Control software is triggered via either external command or per Mission Data File information (such as that contained in the Ambiguity Resolution Matrix). The emitter ID ambiguity reduction system includes Data collection hardware and firmware and Data Analysis OFP software algorithm(s).

Abstract: An emitter ID ambiguity reduction system includes a Mission Data File Ambiguity Resolution matrix that contains both a) the INTEL-based emitter parameters data necessary to break emitter-by-emitter ambiguities, and b) the action(s) the Electronic Warfare (EW) system is to take to collect that data. Control software is triggered via either external command or per Mission Data File information (such as that contained in the Ambiguity Resolution Matrix). The emitter ID ambiguity reduction system includes Data collection hardware and firmware and Data Analysis OFP software algorithm(s).

Abstract: Method and system implemented by a collaborative distributed computational network, and related devices, comprising a plurality of client devices supported by a computational network to cooperatively perform interactive operations in at least one community of practice organized in a hierarchical structure at strategic levels, wherein said method comprises the steps of registering at least one community of practice on the computational network, creating a network of practice; assigning a unique identification code for a device on the network of practice computational network, identifying a user through an unique identification user code; connecting the user to at least one community of network of practice; defining a practice; unfolding the practice in strategic levels of this community of practice; registering the practice on the computational network; locating the practice in organizational or geographical coordinates; registering the localization of practice on the computational network; selecting a templat

Abstract: Method and system implemented by a collaborative distributed computational network, and related devices, comprising a plurality of client devices supported by a computational network to cooperatively perform interactive operations in at least one community of practice organized in a hierarchical structure at strategic levels, wherein said method comprises the steps of registering at least one community of practice on the computational network, creating a network of practice; assigning a unique identification code for a device on the network of practice computational network, identifying a user through an unique identification user code; connecting the user to at least one community of network of practice; defining a practice; unfolding the practice in strategic levels of this community of practice; registering the practice on the computational network; locating the practice in organizational or geo graphical coordinates; registering the localization of practice on the computational network; selecting a templa

Abstract: A semiconductor wafer has a clean, high quality Cu oxide formed at the surface of exposed Cu when an extended non-fabrication process time (such as shipping to an assembly/test site or prolonged storage) is expected.

Abstract: A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.

Abstract: A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.

Abstract: A method of removing photoresist from a surface during the manufacture of an integrated circuit. Organometallic polymers and monomers are formed during the etch of a hard mask material defining the locations of a metal-bearing film, such as tantalum nitride, when photoresist is used to mask the hard mask etch. These organometallic polymers and monomers as formed are not fully cross-linked. A liquid phase solution of sulfuric acid and hydrogen peroxide used to remove the photoresist also removes these not-fully-cross-linked organometallic polymers and monomers, thus preventing the formation of stubborn contaminants during subsequent high temperature processing.

Abstract: A copper interconnect having a transition metal-silicon-nitride barrier (106). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (106). The copper (110) is then deposited over the transition metal-silicon-nitride barrier (108) with good adhesion.

Abstract: A method for forming a single damascene and/or dual damascene interconnect structure, comprising: performing front end processing, depositing copper, annealing the copper, performing CMP planarization, performing a post copper CMP clean process, performing a BTA rinse, performing IPA drying process, performing doping during thermal ramp up and performing remaining back end processing.

Abstract: The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105) located over a semiconductor substrate (110) and an insulating layer (115) located over the circuit feature (105). A protective overcoat (120) is located over the insulating layer (115) and a metal structure (125) is located over the protective overcoat (120). The metal structure (125) is electrically connected to the circuit feature (105) by an interconnect (130). The metal structure (125) is coated with a conductive encasement (135), the conductive encasement (135) terminating at a perimeter (140) of the metal structure (125). Another embodiment of the invention in a method of manufacturing an integrated circuit device (200).

Abstract: The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105) located over a semiconductor substrate (110) and an insulating layer (115) located over the circuit feature (105). A protective overcoat (120) is located over the insulating layer (115) and a metal structure (125) is located over the protective overcoat (120). The metal structure (125) is electrically connected to the circuit feature (105) by an interconnect (130). The metal structure (125) is coated with a conductive encasement (135), the conductive encasement (135) terminating at a perimeter (140) of the metal structure (125). Another embodiment of the invention in a method of manufacturing an integrated circuit device (200).

Abstract: In an integrated device, a via is formed in a substrate layer and a barrier layer is formed on the substrate layer in the via. A seed layer is formed on the barrier layer in the via. The seed layer includes a first material and a second material. The first material provides an ability for the second material to maintain an adherence to the barrier layer.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a dielectric layer (226) in a fixed position relative to the wafer, where the dielectric layer comprises an atomic concentration of each of silicon, carbon, and oxygen. After the forming step, the method exposes (118) the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased. After the exposing step, the method forms a barrier layer (120) adjacent at least a portion of the dielectric layer.

Abstract: A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form a silicon-rich capping layer (108) at the surface of the barrier (106). The copper (110) is then deposited over the silicon-rich capping layer (108) with good adhesion.

Abstract: In an integrated device, a via is formed in a substrate layer and a barrier layer is formed on the substrate layer in the via. A seed layer is formed on the barrier layer in the via. The seed layer includes a first material and a second material. The first material provides an ability for the second material to maintain an adherence to the barrier layer.

Abstract: A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108. A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form a silicon-rich capping layer (108) at the surface of the barrier (106). The copper (110) is then deposited over the silicon-rich capping layer (108) with good adhesion.

Abstract: A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form a silicon-rich capping layer (108) at the surface of the barrier (106). The copper (110) is then deposited over the silicon-rich capping layer (108) with good adhesion.

Abstract: A barrier/liner structure (10) and method. First, a refractory metal/metal nitride layer (12) is formed over a structure (18), for example, by metal-organic CVD (MOCVD). Then, the refractory metal/metal nitride layer (12) is exposed to an organosilane, such as diethylsilane, to obtain a silicon-rich surface layer (14).

Abstract: A copper interconnect having a transition metal-silicon-nitride barrier (106). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (106). The copper (110) is then deposited over the transition metal-silicon-nitride barrier (108) with good adhesion.