Abstract: A direct data placement implementation for a data reassembly process. Data within a protocol data unit is placed directly in preassigned application buffers. The network interface card has buffer space into which message headers, segment headers and indicators of escaped data and size of escaped data are placed. A single buffer can contain this information for a complete PDU (or message) and is handed over to enable the next process to run on a per message basis.

Abstract: A system of switch modules comprises input demultiplexers connected to ports on each of the modules and output multiplexers connected to each of the modules. Each module has output and input interfaces for mesh links and at least one output interface is looped back to an input interface on the same module. The arrangement reduces module-to-module traffic and corresponding increases the transmit bandwidth of a module.

Abstract: A method and apparatus for blocking access of a malfunctioning server to a data storage facility. Characteristics such as IAmAlive signals from a server are monitored and when out of profile a malfunction is indicated and data access of that server is inhibited. Characteristics continue to be monitored for a return from the malfunction. The system is used in a resilient cluster of servers to shut out a malfunctioning sever and enable its recovery to be indicated so as to enable readmittance to the cluster.

Abstract: A storage assembly comprising, a plurality of multi-unit storage devices, such as a plurality of disks in a box, is provided with a failover procedure that does not require hot-swap capability of the units. The individual units are aggregated into a storage array by an aggregation procedure such as RAID. The system has at least one hot spare.

Abstract: A method for distributing addressed data packets from an input channel to a multiplicity of packet queues includes receiving said addressed data packets and, responsive to first hashed addresses, distributing the addressed data packets to said queues in accordance with said first hashed addresses. A first hash function is applied to selected address data of each of said addressed data packets to produce said first hashed addresses. At the same time a succession of different hash functions is applied to said selected address data in each of the packets to produce second hashed addresses and occurrences of each of the second hashed addresses are counted so as to obtain for each of said different hash functions a respective one of a plurality of set of counts, each such set representing the distribution of said packets that would occur in said queues if the respective one of the different hash functions had been applied to said addressed data packets.

Abstract: A system for allowing storage servers that operate on an external file level protocol to be incorporated in a storage network that operates with a block level protocol. A functional unit in a main server aggregator 3 retains a block map referred to files on the file level server. The block map is input to the aggregation layer of the aggregator server as if it were a block level store. Block access requests are mapped back to the relevant file and file offset location and the functional unit sends file protocol access requests to the remote file level server and has a file access acceleration system.

Abstract: A method of transmitting data (1) generated in an upper layer protocol such as iSCSI in a transport protocol such as TCP or SCTP, without requiring separate reads for check code generation and transmission. The upper layer protocol data is read into a transmission engine (5) that calculates the error check codes and inserts them into the transport protocol transmission. To prevent having to recalculate error codes in the event of loss of transmitted data and a retransmission request, the engine preferably also writes the error check codes into the memory so that the can be retrieved if retransmission is necessary.

Abstract: A direct data placement implementation for a data reassembly process Data within a protocol data unit is placed directly in preassigned application buffers The network interface card has buffer space into which message headers, segiment headers and indicators of escaped data and size of escaped data are placed A single buffer can contain this information for a complete PDU (or message) and is handed over to enable the next process to run on a per message basis

Abstract: A scheme for protecting memory stored in a DRAM using a combination of horizontal and vertical parity data to detect and correct errors in a protected space of memory in which code is stored. The DRAM memory of this scheme is architected with the code stored in horizontally contiguous bytes and the vertical parity, generated when the code is compiled, also stored in horizontally contiguous bytes, but in a row of DRAM memory separate from those in which the code is stored.

Abstract: Apparatus for monitoring and controlling data flow ina computer network device having a plurality of parts comprises control means for directly linking ports together on the basis of additional information stored in the control means whereby incoming packets are linked directly to an utput port to achieve high performance. The additional information is stored in one more look-up tables additional to the normal CAm with the or each table addressed by separate processing. This allows the implementation to be in hardware rather than in software.

Abstract: Arbitration means for arbitrating between computer devices A to F which compete for access to a common bus. The system provides cascaded round-robin units. Unit RR1 has ports A, B, C, and X in sequence, with port X coupled to round-robin unit RR2, which has ports D, E, F in sequence. On each cycling of unit RR1 past C to A, unit RR2 is checked and the next one of devices D to F (in the sequence determined by unit RR2) has the opportunity of bus access. A gating circuit 13 can further restrict bus accessing by unit RR2's devices, by timing or counter control. A third round-robin unit can be added coupled to unit RR1 (which would have ports A, B, C, X,Y) or to unit RR2 (which would have ports D, E, F, Y). The assignment of devices to ports can be controllable by a matrix switch and device assignment memory.

Abstract: A data processing system comprising a main memory 10 with a 32-bit longword data bus 11 and an address bus 12, and a link unit 20 using 16-bit shortwords. The link unit has two shortword memories 26 and 28 for descriptor and message shortwords. Descriptor shortwords are exchange individually with the memory 10, residing in the lower halves of longword locations; message shortwords are exchanged with the memory 10 through a concatenation and deconcatenation unit 40 so that they are stored in pairs in longword locations. Unit 20 passes descriptor addresses (with top bit 1) from a register 25 and message addresses (with top bit 0) from a register 27 to the main memory through address processing means 36, which comprises a multiplexer 43 with its two data inputs fed with two versions of the address with a 1-bit shift between them. The top address bit controls the multiplexer, so that the main memory address steps by 1 for every step of a descriptor address or every second step of a message word address.

Abstract: An Ethernet network or other CSMA/CD network includes a hub that is modified to generate a jamming signal on a communication line when a packet received over that line is directed to an unavailable destination. The destination may be unavailable due to full transmit buffers, full receive buffers, or congestion in other parts of the hub architecture. Jamming is detected by the source node as a collision and causes retransmission of the packet from the source node. The decision to jam may include a determination of the packet's priority which may be determined based on the packet's destination or source address.

Abstract: A logic circuit for use as an arbiter to arbitrate among N devices of a computer system for access to a shared resource. The arbiter generates state variables to represent arbitration win information. The state variables are generated through the use of request for arbitration signals input to the arbiter, present values of the state variables and internally generated intermediate arbitration win signals to provide a cost effective, efficient implementation of the logic required for the arbitration in a smaller physical solution for the arbitration logic.