Abstract: A highly parallel microprocessor using a logic gating structure and a microinstruction organization which permits direct access by each of the microprocessor components to a tri-bus system. Operation is defined by a single phase clock, during which all portions of a microinstruction are executed. The system further permits overlap operation for microprocessor instructions, thereby allowing for the fetching of a next instruction while executing a current instruction. The use of general purpose, non-dedicated registers is contemplated, thereby to avoid the need for multi-phase clocking.

Abstract: A microprocessor with a bus structure for carrying address and data signals wherein an address may be modified by an index value for indirect addressing by deriving said index value from an index register or a control word field. Immediate addressing is provided on branch instructions by providing two separate incrementing paths to avoid loss of a machine cycle during branch.

Abstract: A microprogrammable data processor comprising a generalized three-bus archictecture wherein the functional processing elements are connected between the busses by means of tri-state logic elements which allow the elements to selectively drive, receive from, or present a high impedance to the busses under control of a microprogram. The device includes an input-output system in which the input/output device may have access to all three busses, two for data and for address inputs and the third for receiving output data. The busses may be multifunction busses for carrying either data or address signals.The device utilizes a single phase clock and performs operations in a highly parallel manner.