Abstract: A single button contrast control which can bi-directionally adjust a contrast function in one of two directions so as to increase or decrease the contrast of a display. An interrupt generator generates an interrupt for each user activation of a single button control key. A control circuit incrementally adjusts the contrast function in accordance with the interrupts generated. If no interrupts are generated within a predetermined period of time following a previous interrupt, the control circuit changes the direction in which the contrast is incrementally adjusted so that the next time a user activates the single button control key the control will be adjusted in the other direction.

Abstract: A system for upgrading a personal computer includes a motherboard having upgrade sockets for upgrading the CPU and the clock oscillator without the need to remove any components. The system includes sensing circuitry for detecting the type of component plugged into the upgrade socket and circuitry for disabling the upgraded component. In addition, the system includes software for reconfiguring various signals depending on the particular upgrade plugged into the upgrade socket. By providing a system that can be upgraded by merely inserting a newer components, upgrades can be performed rather quickly. In addition, the upgrade system allows the end user a plurality of upgrade options while at the same time allows the end user to take advantage of declining CPU prices.

Abstract: A line switch for a digital telephone switching system utilizes distributed processing. The line switch comprises one or more switch modules. Each switch module is coupled to a central office switching system via one or more PCM lines which utilize common channel signaling. Each switch module comprises groups of line circuits, each line circuit being coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. A first processor is utilized to communicate with the central office switching system is provided to control clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit.A test bus is routed to the line circuits. The third processor may be utilized to automatically measure and adjust various transmission parameters.

Abstract: A line switch for a digital telephone switching system utilizes distributed processing. The line switch comprises one or more switch modules. Each switch module is coupled to a central office switching system via one or more PCM lines which utilize common channel signaling. Each switch module comprises groups of line circuits, each line circuit being coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. A first processor is utilized to communicate with the central office switching system and to coordinate the operations within the line switch module. A second processor is provided to control clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit. A busing arrangement is provided within the line switch such that both control information and PCM voice data are routed throughout the line switch.

Abstract: A line switch for a digital telephone switching system utilizes distributed processing. The line switch comprises one or more switch modules. Each switch module is coupled to a central office switching system via one or more PCM lines which utilize common channel signaling. Each switch module comprises groups of line circuits, each line circuit being coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. A first processor is utilized to communicate with the central office switching system and to coordinate the operations within the line switch module. A second processor is provided to control clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit. A busing arrangement is provided within the line switch such that both control information and PCM voice data are routed throughout the line switch.