Abstract: A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design.

Abstract: A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design.

Abstract: A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor.

Abstract: A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor.

Abstract: A technique for preventing high current shorts through I/O pads of an integrated circuit during power up and power down is presented. In accordance with the invention, the voltage levels of the core power supply that powers the internal circuitry of the integrated circuit and the I/O power supply that powers the input and/or output pad drivers is monitored to detect the condition wherein the core power supply is powered down and the I/O power supply is powered up. Upon detection of this condition, the pad drivers are disabled, preferably by disabling the pre-drivers that generate the pre-drive signals that drive the output driver devices. In a preferred embodiment, the process/voltage/temperature adjustment circuitry is leveraged to disable the output pads during power up and down.

Abstract: An electrostatic discharge (ESD) structure for use in an integrated circuit (IC). The ESD structure comprises a metallic resistor and a metallic capacitor that are electrically coupled in series to form a resistor-capacitor (RC) component having an appropriate RC time constant. The RC component maintains a level of charge between ground and a shunt node to ensure that, during an ESD event, electrostatic charge on a power supply, VDD, associated with the ESD structure is shunted via a shunt path from said power supply VDD to said ground. By using metal to create the metal resistor and capacitor, charge leakage problems that result from parasitic capacitance associated with using an RC component comprised of either a poly, active, or nwell resistor in combination a diode are eliminated. By eliminating such charge leakage problems, a more reliable RC component, and thus a more reliable RC time constant, are obtained.

Abstract: A high gain, low input capacitance clock buffer includes a plurality of transistors configured to supply an inverted representation of an input reference signal by alternatively switching to provide the output. While either of the transistors is operating to switch the input clock signal, the other transistor is in a stable state. Furthermore, by using n-type FET's, significant power reduction and space savings may be achieved.

Abstract: A circuit and method for reducing error in a delay locked loop (DLL) in which a plurality of outputs, each establishing a boundary between two consecutive phases, is accomplished by averaging an error present in one of the outputs over at least two phases established by the outputs. A pair of inverters are used to drive fight during a definable time period, which enables the circuitry to average the error over at least two phases, thus distributing the error that was present in one phase over at least two phases.