Abstract: Keyboard input circuitry for use in a microcomputer continuously scans a keyboard having a plurality of keys organized into K columns and J rows. A counter under control of a reset signal and clock signal, sequentially provides K output signals for enabling the K column conductors. When a key in the Kth column and Jth row is depressed, the Kth output signal from the counter will be coupled to the Jth row. Thus, the logical state of the J row conductors will determine whether or not a key of the enabled column of keys is depressed or not. The microcomputer includes a register, a memory, and a peripheral interface adapter circuit. The microcomputer provides the reset signal and clock signal to the register and to the counter by way of the peripheral interface adapter circuit, for maintaining synchronism between the register and counter.

Abstract: An addressing circuitry for a dot matrix vertical scan plasma display includes a character row counter and a character column counter, a random access memory, a dot pattern generator, a parallel to series shift register, and a driver for the display. The addressing circuitry is responsive to a processor. Alpha-numeric digital characters to be displayed are read out of the memory in sequence in response to a sequence signal from the character row counter and the character column signal output. The words read out of the memory are converted into dot matrix pattern by the dot pattern generator and displayed on the plasma display via the parallel to serial shift register and driver. An offset adder is used when the number of character rows and the number of characters per row of the display are other than binary progression numbers in generating a sequence signal. The offset adder is interposed between the random access memory and the row and column outputs.