Abstract: A system and method for centrally logging and aggregating miscompares on chip during a memory test. The method includes performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm. The method includes generating miscompare results responsive to performing the memory test on the one or more memory banks of the memory device. The method includes determining failure diagnostic information based on the miscompare results. The method includes generating an error packet comprising the failure diagnostic information and the miscompare results. The method includes placing the error packet in a queue of a plurality of error packets to generate a queued error packet.

Abstract: A system and method for centrally logging and aggregating miscompares on chip during a memory test. The method includes performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm. The method includes generating miscompare results responsive to performing the memory test on the one or more memory banks of the memory device. The method includes determining failure diagnostic information based on the miscompare results. The method includes generating an error packet comprising the failure diagnostic information and the miscompare results. The method includes placing the error packet in a queue of a plurality of error packets to generate a queued error packet.

Abstract: The present invention provides a system for testing a memory array and corresponding support circuitry. The present invention provides a highly efficient testing mode to be entered that allows any type of advanced testing to be performed on the memory array without regard to the restrictions imposed by the various status flags that may be present. The testing mode can be entered by a completely user-defined mechanism. During this testing mode, the user has complete control over the contents of the memory array and can also have complete control over the positioning of the write word line with respect to the read word line without, for example, any write-read word line pointer equality signals being generated. In one example of the present invention used in a FIFO, testing times required for data retention testing are reduced from approximately six seconds to approximately 500.mu.