Abstract: A distributed memory addressing system has a plurality of separate processing elements. Each processing element has at least one CPU. A shared memory is utilized to store data to be used by the separate processing elements, as required. A high bandwidth interface interconnects processing elements and the shared memory. The high bandwidth interface is configured so as to provide non-blocking access to the shared memory for each of the processing elements.

Abstract: A memory interface device for facilitating electrical communication between distributed memory and a plurality of processors has a memory interface circuit configured to interface the memory interface device to at least one random access memory, an address generator circuit configured to generate addresses for data stored within the random access memories and a processor interface circuit configured to interface the memory interface device to a plurality of processors. Interfacing the memory interface device to both the random access memories and the plurality of processors facilitates simultaneous non-interruptible access by all of the processors to data stored in the random access memories.