Abstract: The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.

Abstract: A radio apparatus with a phase locked loop is disclosed. The apparatus contains a phase detector with first and second inputs, where the first input receiving a reference frequency signal and the second input receives a controllable frequency signal that is controlled by a tuning voltage. Also included is, a loop filter for filtering the output of the phase detector, circuitry for decoding when a phase difference at the inputs of the phase detector exceeds a predetermined value, and a filter bypass circuit. This circuit bypasses operation of the loop filter when the difference at the inputs of the phase detector exceeds a predetermined value, allowing fast voltage changes of the tuning voltage, and providing a short lock time for the phase locked loop.

Abstract: A process for fabricating a high voltage CMOS transistor having a non-self aligned implanted channel which permits the operation of the device at high voltages. The non-self aligned implanted channel does not require alignment with the gate electrode of the CMOS device, but is accurately implanted early in the fabrication of the device through reliance on direct wafer stepper technology. As a result, the non-self aligned implanted channel does not require a high temperature drive, such that fabrication of the transistor is compatible with VLSI and ULSI processes, and the transistor can be up-integrated onto logic integrated circuits. Accuracy of the placement of the non-self aligned implanted channel provides for a shorter channel length, which enables the device to be highly area efficient while also increasing the current capability of the device.

Abstract: A current limit circuit for limiting current flow through a load circuit. The amount of current flowing in the circuit is sensed by a current sensing resistor. The circuit includes a P-channel field effect transistor and an NPN bipolar transistor. When current sensed by the resistor attains a current limit value, the field effect transistor is turned on and its output current is amplified by the NPN transistor. The emitter of the NPN transistor is connected to the gate of another P-channel field effect transistor which is connected to the load circuit.

Abstract: This invention relates to a waveshaping circuit for producing a bus output voltage signal having a substantially sinusoidal rising transition from a low voltage level to a high voltage level in response to the rising edge of a data input signal, and a substantially sinusoidal falling transition from said high voltage level to said low voltage level, in response to the falling edge of said data input signal. The circuit uses AC coupling to control the waveshaping. This allows the circuit to operate with a large ground offset voltage difference between circuit ground and bus ground. An exponential current source provides a current to a regulator bus driver which charges and discharges a capacitor in response to the the rising edge or falling edge on the data input signal.