Abstract: Fault state recovery using predefined configurations, including: determining that a first node of a plurality of nodes has failed; identifying, based on the first node failing, a failure state from a plurality of predefined failure states each corresponding to a different combination of one or more failed nodes, wherein each of the plurality of predefined failure states corresponds to a respective configuration of a plurality of configurations; and applying the respective configuration corresponding to the identified failure state, wherein applying the respective configuration comprises at least one of: updating one or more memory mapping tables based on the respective configuration or copying data from memory locations used based on a previous configuration to memory locations indicated in the respective configuration.

Abstract: Shared memory access in a distributed system, including: receiving a memory access request associated with a time value; determining, based on the time value, an entry in a translation lookaside buffer (TLB); and determining, based on the entry, whether to allow the memory access request.

Abstract: Fault state transitions in an autonomous vehicle may include determining that a first node of a plurality of nodes has failed; determining, in response to the first node failing, a failure state; determining, based on the failure state, a configuration for the plurality of nodes excluding the first node; and applying the configuration.

Abstract: Shared memory access in a distributed system, including: determining, in response to a memory access request, based on a time value, an entry in an access permissions table by: determining, based on a modulo of the time value and a number of entries in the access permissions table, a table index; determining, based on the table index, the entry; and determining, based on the entry, whether to allow the memory access request.

Abstract: Shared memory access in a distributed system, including: determining, in response to a memory access request, based on a time value, an entry in an access permissions table by: determining, based on a modulo of the time value and a number of entries in the access permissions table, a table index; determining, based on the table index, the entry; and determining, based on the entry, whether to allow the memory access request.

Abstract: Timed memory access, including: determining, in response to a memory access request, based on a time value, an entry in an access permissions table; and determining, based on the entry, whether to allow the memory access request that can include determining, based on a modulo of the time value and a number of entries in the access permissions table, a table index and determining, based on the table index, the entry.

Abstract: Error handling in an autonomous vehicle, including: receiving, by a control system of the autonomous vehicle, from an automation computing system, a remediation sequence comprising a first plurality of operational commands determined to bring the autonomous vehicle to a stop; determining, by the control system, that the error state associated with the autonomous vehicle has been reached; and executing, by the control system, in response to the error state being reached, the first plurality of operational commands.

Abstract: Timed memory access, including: determining, in response to a memory access request, based on a time value, an entry in an access permissions table; and determining, based on the entry, whether to allow the memory access request that can include determining, based on a modulo of the time value and a number of entries in the access permissions table, a table index and determining, based on the table index, the entry.

Abstract: Fault state transitions in an autonomous vehicle may include determining that a first node of a plurality of nodes has failed; determining, in response to the first node failing, a failure state; determining, based on the failure state, a configuration for the plurality of nodes excluding the first node; and applying the configuration.

Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Abstract: In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Abstract: An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.

Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Abstract: In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Abstract: In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Abstract: There is provided a method for routing packets on a linear of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves.

Abstract: An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.

Abstract: There is provided a method for routing packets on a linear array of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves.

Abstract: An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance wit

Abstract: A segregated waste disposal device is disclosed which includes a plurality of waste receptacles provided in a main housing, each of the plurality of waste receptacles receiving one of a plurality of distinct waste products, respectively, including glass and metal. An opening within the main housing receives at least one of the glass and metal waste, and the weighted lid connected to the main housing crushes waste deposited into the opening. The lid may be opened either by hydraulic or mechanical spring mechanisms and a grate member provided within the opening and beneath the weighted lid allows crushed glass to free-fall therethrough into a predetermined receptacle. A sweep arm sweeps remaining crushed waste off of the grate into a waste receptacle other than a waste receptacle containing crushed glass.