Patents by Inventor Richard A. Uhlig

Richard A. Uhlig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method to deprivilege components of a virtual machine monitor
    Patent number: 7757231
    Abstract: In some embodiments, the invention involves a system to deprivilege components of a virtual machine monitor and enable deprivileged service virtual machines (SVMs) to handle selected trapped events. An embodiment of the invention is a hybrid VMM operating on a platform with hardware virtualization support. The hybrid VMM utilizes features from both hypervisor-based and host-based VMM architectures. In at least one embodiment, the functionality of a traditional VMM is partitioned into a small platform-dependent part called a micro-hypervisor (MH) and one or more platform-independent parts called service virtual machines (SVMs). The micro-hypervisor operates at a higher virtual machine (VM) privilege level than any SVM, while the SVM and other VMs may still have access to any instruction set architecture (ISA) privilege level. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: July 13, 2010
    Assignee: Intel Corporation
    Inventors: Andrew V. Anderson, Steven M. Bennett, Erik Cota-Robles, Alain Kägi, Gilbert Neiger, Rajesh S. Madukkarumukumana, Sebastian Schoenberg, Richard Uhlig, Michael A. Rothman, Vincent J. Zimmer, Stalinselvaraj Jeyasingh
  • Direct memory access (DMA) address translation between peer input/output (I/O) devices
    Publication number: 20100100649
    Abstract: A method and apparatus is described herein for supporting direct memory accesses between peer I/O devices. It is determined whether a guest physical address (GPA) referenced by an access generated from an I/O device, is within a range of GPAs associated with local I/O devices based at least in part on a GPA base and a GPA window size. If the GPA is within the window, then the GPA is translated to an HPA based at least in part on a base HPA associated with a local device and then forwarded to that local device. However, if the GPA is not within the window, then the access is forwarded upstream.
    Type: Application
    Filed: December 22, 2009
    Publication date: April 22, 2010
    Inventors: Rajesh Madukkarumukumana, James A. Sutton, II, Ioannis Schoinas, Richard Uhlig
  • SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE
    Publication number: 20100011186
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Application
    Filed: June 30, 2009
    Publication date: January 14, 2010
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh Madukkaraumukumana, Camron Rust, Sebastian Schoenberg
  • Performance enhancement of address translation using translation tables covering large address spaces
    Publication number: 20100011187
    Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.
    Type: Application
    Filed: September 1, 2009
    Publication date: January 14, 2010
    Inventors: Ioannis Schoinas, Gilbert Neiger, Rajesh Madukkarumukumana, Ku-Jei King, Richard Uhlig, Achmed Rumi Zahir, Koichi Yamada
  • Method and apparatus for facilitating recognition of an open event window during operation of guest software in a virtual machine environment
    Patent number: 7620949
    Abstract: In one embodiment, a method includes transitioning control to a virtual machine (VM) upon receiving a request from a virtual machine monitor (VMM), determining that the request to transition control is associated with a request to be informed of an open event window, performing an event window check to determine whether an even window of the VM is open, and transitioning control to the VMM if the event window check indicates that the event window of the VM is open.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: November 17, 2009
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig
  • METHOD AND APPARATUS FOR FACILITATING RECOGNITION OF AN OPEN EVENT WINDOW DURING OPERATION OF GUEST SOFTWARE IN A VIRTUAL MACHINE ENVIRONMENT
    Publication number: 20090265709
    Abstract: In one embodiment, a method includes transitioning control to a virtual machine (VM) upon receiving a request from a virtual machine monitor (VMM), determining that the request to transition control is associated with a request to be informed of an open event window, performing an event window check to determine whether an even window of the VM is open, and transitioning control to the VMM if the event window check indicates that the event window of the VM is open.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Inventors: STEVEN M. BENNETT, Andrew V. Anderson, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig
  • Maintaining Processor Resources During Architectural Events
    Publication number: 20090248951
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Application
    Filed: June 12, 2009
    Publication date: October 1, 2009
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard Uhlig, Gilbert Neiger, Robert T. George
  • Transitioning between virtual machine monitor domains in a virtual machine environment
    Patent number: 7581219
    Abstract: Techniques for handling certain virtualization events occurring within a virtual machine environment. More particularly, at least one embodiment of the invention pertains to handling events related to the sub-operating system mode using a dedicated virtual machine monitor (VMM) called the system management mode VMM (SVMM), which exists in a separate portion of memory from a main virtual machine monitor (MVMM) used to handle virtualization events other than those related to the sub-operating system mode. In at least one embodiment, a technique for initializing and managing transitions to and from the SVMM is disclosed.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Steven M. Bennett, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, III
  • Maintaining Processor Resources During Architectural Events
    Publication number: 20090193222
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Application
    Filed: March 30, 2009
    Publication date: July 30, 2009
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard Uhlig, Gilbert Neiger, Robert T. George
  • Maintaining processor resources during architectural events
    Patent number: 7562179
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard Uhlig, Gilbert Neiger, Robert T. George
  • Synchronizing a translation lookaside buffer to an extended paging table
    Patent number: 7555628
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: June 30, 2009
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh Madukkarumukumana Sankaran, Camron Rust, Sebastian Schoenberg
  • Method and apparatus for a guest to access a memory mapped device
    Patent number: 7506121
    Abstract: Embodiments of apparatuses, methods, and systems for guests to access memory mapped devices are disclosed. In one embodiment, an apparatus includes evaluation logic and exit logic. The evaluation logic is to determine, in response to an attempt of a guest to access a device using a memory address mapped to the device and based on an access type, whether the access is allowed. The exit logic is to transfer control to a host if the evaluation logic determines that the access is not allowed.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Andrew V. Anderson, Steven M. Bennett, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Rajesh S. Parthasarathy, Sebastian Schoenberg
  • Address translation for input/output devices using hierarchical translation tables
    Patent number: 7444493
    Abstract: An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Ioannis Schoinas, Rajesh Madukkarumakumana, Gilbert Neiger, Richard Uhlig, Ku-jei King
  • VIRTUAL INTERRUPT PROCESSING IN A LAYERED VIRTUALIZATION ARCHITECTURE
    Publication number: 20080244571
    Abstract: Embodiments of apparatuses, methods, and systems for processing virtual interrupts in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes virtual machine entry logic, recognition logic, and evaluation logic. The virtual machine entry logic is to transfer control of the apparatus from a host to a guest. The recognition logic is to recognize a virtual interrupt request. The evaluation logic is to determine whether to transfer control from the guest to an intervening monitor in response to the virtual interrupt request.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Use of multiple virtual machine monitors to handle privileged events
    Patent number: 7424709
    Abstract: In one embodiment, a method for handling privileged events in a virtual machine environment includes detecting an occurrence of a privileged event, determining which one of multiple virtual machine monitors (VMMs) is to handle the privileged event, and transitioning control to this VMM.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Steven M. Bennett, Alain Kägi, Stalinselvaraj Jeyasingh, Andrew V. Anderson, Richard Uhlig, Erik Cota-Robles, Scott Rodgers, Lawrence Smith
  • INTERRUPT REMAPPING BASED ON REQUESTOR IDENTIFICATION
    Publication number: 20080162762
    Abstract: Embodiments of apparatuses, methods, and systems for interrupt remapping based on requestor identification are disclosed. In one embodiment, an apparatus includes look-up logic, and comparison logic. The look-up logic is to look-up an entry associated with an interrupt request in a data structure. The comparison logic is to compare an identifier of the requestor to a source value in the entry.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Gilbert Neiger, Rajesh Sankaran Modukkarumukumana, Sridhar Muthrasanallur, Sebastian Schoenberg, Richard A. Uhlig
  • Virtualizing memory type
    Patent number: 7370160
    Abstract: A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 6, 2008
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Steven M. Bennett, Andrew V. Anderson, Dion Rodgers, David Koufaty, Richard A. Uhlig, Camron B. Rust, Larry O. Smith, Rupin H. Vakharwala
  • Providing support for single stepping a virtual machine in a virtual machine environment
    Patent number: 7356735
    Abstract: Methods and systems to provide support for single stepping a virtual machine in a virtual machine environment are disclosed. An exemplary method may include receiving a request to transition control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a single-stepping indicator is set to a single stepping value, and transitioning control to the VM. Further, if an execution of a first instruction in the VM completes successfully, control is transitioned to the VMM following the successful completion of the execution of the first instruction.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: April 8, 2008
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kägi, Gilbert Neiger, Richard Uhlig, Sanjoy K. Mondal, Jason Brandt
  • Fault processing for direct memory access address translation
    Patent number: 7340582
    Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 4, 2008
    Assignee: Intel Corporation
    Inventors: Rajesh Madukkarumukumana, Ioannis Schoinas, Ku-jei King, Balaji Vembu, Gilbert Neiger, Richard Uhlig
  • Synchronizing a translation lookaside buffer to an extended paging table
    Publication number: 20080046679
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Application
    Filed: August 15, 2006
    Publication date: February 21, 2008
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh Madukkarumukumana, Camron Rust, Sebastian Schoenberg