Abstract: A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner—based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.

Abstract: A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner—based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.