Abstract: An array of bottom-emitting VCSELs, with its substrate still intact, is tested by means of a probe that includes an optoelectronic array, which is aligned and coupled to the top surface of the VCSEL array. The probe is aligned to the VCSEL array just once. The optoelectronic array includes driver circuits for energizing the VCSELs and the photodetection circuits in a predetermined sequence for detecting the back emission that leaks through the top mirror of each VCSEL. In another embodiment, this probe and method are applied to testing bottom-emitting VCSELs one at a time. The VCSELs may discrete devices or part of an array. In accordance with another aspect of our invention, an array of bottom-emitting VCSELs, with its substrate still in intact, is tested by means of a probe that includes separate electronic and photodetection arrays. The probe is aligned to the VCSEL array just once.

Abstract: An array of bottom-emitting VCSELs, with its substrate still intact, is tested by means of a probe that includes an optoelectronic array, which is aligned and coupled to the top surface of the VCSEL array. The probe is aligned to the VCSEL array just once. The optoelectronic array includes driver circuits for energizing the VCSELs and the photodetection circuits in a predetermined sequence for detecting the back emission that leaks through the top mirror of each VCSEL. In another embodiment, this probe and method are applied to testing bottom-emitting VCSELs one at a time. The VCSELs may discrete devices or part of an array. In accordance with another aspect of our invention, an array of bottom-emitting VCSELs, with its substrate still in intact, is tested by means of a probe that includes separate electronic and photodetection arrays. The probe is aligned to the VCSEL array just once.

Abstract: An array of bottom-emitting VCSELs, with its substrate still intact, is tested by means of a probe that includes an optoelectronic array, which is aligned and coupled to the top surface of the VCSEL array. The probe is aligned to the VCSEL array just once. The optoelectronic array includes driver circuits for energizing the VCSELs and the photodetection circuits in a predetermined sequence for detecting the back emission that leaks through the top mirror of each VCSEL. In another embodiment, this probe and method are applied to testing bottom-emitting VCSELs one at a time. The VCSELs may discrete devices or part of an array. In accordance with another aspect of our invention, an array of bottom-emitting VCSELs, with its substrate still in intact, is tested by means of a probe that includes separate electronic and photodetection arrays. The probe is aligned to the VCSEL array just once.

Abstract: An array of bottom-emitting VCSELs, with its substrate still intact, is tested by means of a probe that includes an optoelectronic array, which is aligned and coupled to the top surface of the VCSEL array. The probe is aligned to the VCSEL array just once. The optoelectronic array includes driver circuits for energizing the VCSELs and the photodetection circuits in a predetermined sequence for detecting the back emission that leaks through the top mirror of each VCSEL. In another embodiment, this probe and method are applied to testing bottom-emitting VCSELs one at a time. The VCSELs may discrete devices or part of an array. In accordance with another aspect of our invention, an array of bottom-emitting VCSELs, with its substrate still in intact, is tested by means of a probe that includes separate electronic and photodetection arrays. The probe is aligned to the VCSEL array just once.

Abstract: A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.

Abstract: A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.

Abstract: A process for forming a semiconductor wafer with a flat surface is disclosed. In the process, a bare semiconductor wafer that has been sawed from an ingot is provided. A layer of planarization material is formed on at least one major surface of the semiconductor wafer. The layer of planarization material is placed into contact with a respective object having a flat surface. Pressure is applied to cause the planarization material to flow and impart a planar, surface to the layer of planarization material. The planarization material is then hardened. The flat surface is separated from contact with the respective layer of hardened material. The surface flatness is then transferred into the underlying substrate surface.

Abstract: The specification describes techniques for soldering IC chips, or other components, to interconnection substrates using a patterned epoxy layer to define the solder interconnections. The epoxy layer is photodefined to form openings that expose the bonding sites on the IC chip (or alternatively the interconnect substrate). Solder paste is deposited in the openings. With the IC chip and the interconnect substrate aligned together, the solder paste is heated to reflow the solder and solder bond the IC chip to the substrate. Heating is continued to cure the epoxy, which serves the function of the conventional underfill. The shape of the solder interconnection is defined by the lithographically formed openings, and the interconnections can be made with very fine pitch. The application of the epoxy underfill in this manner assures complete filling of the gap between the IC chip and the interconnection substrate.

Abstract: A battery charging system for cellular telephones or other portable devices is incorporated into a clock radio. A user is enabled to specify a time-of-day at which s/he wants to be reminded to insert the rechargeable battery into the charging system if re-charging is needed. No alarm is generated if the battery is already in the charging system at the appointed time. A low power radio frequency signal attempts to interrogate the portable device on the assumption that it is within radio range at that time so as to determine the current battery charge status at about the time that the alarm would be generated. If the charging system receives a return signal from the portable device which indicates, or from which it can be determined, that charging is not needed, then the alarm is not generated after all. Otherwise, the alarm is, in fact generated.