Patents by Inventor Richard Allen Bailey
Richard Allen Bailey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11495607Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.Type: GrantFiled: August 7, 2018Date of Patent: November 8, 2022Assignee: Texas Instruments IncorporatedInventors: Huang-Chun Wen, Richard Allen Bailey, Antonio Guillermo Acosta, John A. Rodriguez, Scott Robert Summerfelt, Kemal Tamer San
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Patent number: 10424361Abstract: A method of generating a random number from an electronic circuit memory and/or a system with the electronic circuit memory. The memory comprises a block of ferroelectric two transistor, two capacitor (2T-2C), memory cells. The method comprises: (i) first, writing a predetermined programming pattern to the block cells in a one transistor, one-capacitor (1T-1C) mode, thusly writing, per cell, a same data state to both a first and second sub-cell of the cell; (ii) second, reading the cells in a 2T-2C mode to generate a random number comprising a random bit from each of the cells; (iii) third, restoring the random number into the cells in a 2T-2C mode, thusly writing, per cell, a complementary data state to both a first and second sub-cell of the cell, responsive to a respective random number bit; and fourth, imprinting the random number in each cell in the block.Type: GrantFiled: April 30, 2018Date of Patent: September 24, 2019Assignee: Texas Instruments IncorporatedInventors: John Anthony Rodriguez, Richard Allen Bailey
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Publication number: 20190252016Abstract: A method of generating a random number from an electronic circuit memory and/or a system with the electronic circuit memory. The memory comprises a block of ferroelectric two transistor, two capacitor (2T-2C), memory cells. The method comprises: (i) first, writing a predetermined programming pattern to the block cells in a one transistor, one-capacitor (1T-1C) mode, thusly writing, per cell, a same data state to both a first and second sub-cell of the cell; (ii) second, reading the cells in a 2T-2C mode to generate a random number comprising a random bit from each of the cells; (iii) third, restoring the random number into the cells in a 2T-2C mode, thusly writing, per cell, a complementary data state to both a first and second sub-cell of the cell, responsive to a respective random number bit; and fourth, imprinting the random number in each cell in the block.Type: ApplicationFiled: April 30, 2018Publication date: August 15, 2019Inventors: John Anthony Rodriguez, Richard Allen Bailey
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Publication number: 20180374861Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.Type: ApplicationFiled: August 7, 2018Publication date: December 27, 2018Inventors: Huang-Chun Wen, Richard Allen Bailey, Antonio Guillemo Acosta, John A. Rodriguez, Scott Robert Summerfelt, Kemal Tamer San
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Patent number: 10153053Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.Type: GrantFiled: October 19, 2017Date of Patent: December 11, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sunil Kumar Dusa, Richard Allen Bailey, Archana Venugopal, John Anthony Rodriguez, Michael Allen Ball
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Publication number: 20180040381Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.Type: ApplicationFiled: October 19, 2017Publication date: February 8, 2018Inventors: Sunil Kumar Dusa, Richard Allen Bailey, Archana Venugopal, John Anthony Rodriguez, Michael Allen Ball
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Patent number: 9824769Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.Type: GrantFiled: May 4, 2016Date of Patent: November 21, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sunil Kumar Dusa, Richard Allen Bailey, Archana Venugopal, John Anthony Rodriguez, Michael Allen Ball
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Publication number: 20170018311Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.Type: ApplicationFiled: May 4, 2016Publication date: January 19, 2017Inventors: Sunil Kumar Dusa, Richard Allen Bailey, Archana Venugopal, John Anthony Rodriguez, Michael Allen Ball
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Publication number: 20160086960Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.Type: ApplicationFiled: June 2, 2015Publication date: March 24, 2016Inventors: Huang-Chun Wen, Richard Allen Bailey, Antonio Guillermo Acosta, John A. Rodriguez, Scott Robert Summerfelt, Kemal Tamer San
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Patent number: 7149137Abstract: The present invention facilitates evaluation of ferroelectric memory devices. A ferroelectric memory device is fabricated that comprises memory cells comprising ferroelectric capacitors (802). A short delay polarization value is obtained (804) by writing a data value, performing a short delay, and reading the data value. A long delay polarization value is obtained (806) by again writing the data value, performing a long delay, and again reading the data value. The short delay and long delay polarization values are compared (808) to obtain a data retention lifetime for the ferroelectric memory device. The obtained data retention lifetime is compared with acceptable values (810) and, if deemed unacceptable, avoids unnecessary performance of thermal bake data retention lifetime testing.Type: GrantFiled: December 30, 2004Date of Patent: December 12, 2006Assignee: Texas Instruments IncorporatedInventors: John Anthony Rodriguez, Richard Allen Bailey