Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

Abstract: A plasma-based ashing process for surface conditioning and material modification to improve bond pad metallurgical properties as well as semiconductor device performance. Residue materials generated in a removal process at a process layer having recessed features with Ni—Pd surfaces are ashed in a plasma reactor to reduce defect count and improve surface conditioning associated with bond pads of the semiconductor device.

Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Abstract: Disclosed is an under bump metallization structure including a plurality of metal or metal alloy layers formed on chip bond pads with improved reliability due to a sacrificial metal oxide and the methods of making the under bump metallization structures. A barrier layer is formed over a bond pad. A seed layer is formed over the barrier layer. A bump resist pattern is formed exposing an area over the bond pad and a metal layer is electroplated on the seed layer.

Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Abstract: Disclosed is an under bump metallization structure including a plurality of metal or metal alloy layers formed on chip bond pads with improved reliability due to a sacrificial metal oxide and the methods of making the under bump metallization structures.

Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Abstract: A method of manufacturing a semiconductor device that comprises forming an insulating layer over a semiconductive substrate 110 and forming a copper interconnect. Forming the interconnect includes etching an interconnect opening in the insulating layer and filling the opening with copper plating. Filling with copper plating includes using a first and second ECD. An electrolyte solution of the first and second ECD contains organic additives, and a current of the first ECD is greater than a current of the second ECD.

Abstract: According to one embodiment of the invention, a method for providing improved layer adhesion in a semiconductor is provided. The method includes forming a dielectric layer. The method also includes forming a layer of metal in direct contact with the dielectric layer. The method also includes directly exposing the layer of metal, after forming the layer of metal, to plasma at a power level sufficient to penetrate through the layer of metal and reach the dielectric layer.

Abstract: According to one embodiment of the invention, a method for providing improved layer adhesion in a semiconductor is provided. The method includes forming a dielectric layer. The method also includes forming a layer of metal in direct contact with the dielectric layer. The method also includes directly exposing the layer of metal, after forming the layer of metal, to plasma at a power level sufficient to penetrate through the layer of metal and reach the dielectric layer.