Abstract: A modular heavy load battery test system is provided. The system includes a heavy load module and a battery tester. The heavy load module includes a housing, first and second lengths of high-resistivity, large-gauge wire arranged on respective upper and lower surfaces of a heat-resistant support plate, a switch and at least one cooling fan. The battery tester includes a housing, a microcontroller and a set of battery charging wires. The microcontroller selects the configuration of the first and second wires and provides the control signal to the heavy load module, while the switch selectively connects the first and second wires to the battery tester based upon the control signal.

Abstract: An inductive battery charging system for a handheld service tool is provided. The system includes a battery charger and a handheld service tool. The battery charger has a primary coil enclosed within a housing, and which is coupled to a power source. The service tool includes a secondary coil, enclosed within a housing, that provides at least 100 mA of inductively-generated alternating current, a rectifier, a linear voltage regulator, a battery charge controller and a battery.

Abstract: A modular heavy load battery test system is provided. The system includes a heavy load module and a battery tester. The heavy load module includes a housing, first and second lengths of high-resistivity, large-gauge wire arranged on respective upper and lower surfaces of a heat-resistant support plate, a switch and at least one cooling fan. The battery tester includes a housing, a microcontroller and a set of battery charging wires. The microcontroller selects the configuration of the first and second wires and provides the control signal to the heavy load module, while the switch selectively connects the first and second wires to the battery tester based upon the control signal.

Abstract: A FIFO memory system exhibits data processing capabilities by the inclusion therein of a digital signal processor and an associated dynamic random access memory. The digital signal processor provides significant data processing on the fly while the dynamic random access memory array provides additional buffering capability. Input and output FIFOs are connected to the data and address bussed of the digital signal processor. The control of the digital signal processor is via a host processor connected to the digital signal processor by a serial communication link.