Patents by Inventor Richard Anthony LANE

Richard Anthony LANE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Speculative interrupt signalling
    Patent number: 10102160
    Abstract: A data processing system includes an interrupt controller having a priority level arbitrator and trigger circuitry. The priority level arbitrator and the trigger circuitry operate in parallel to process interrupt signals received by an interrupt signal receiver. The trigger circuitry generates a trigger signal initiating interrupt processing before the priority level arbitrator has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 16, 2018
    Assignee: ARM LIMITED
    Inventors: Michael Kennedy, Simon John Craske, Andrew Turner, Richard Anthony Lane
  • Interrupt signal arbitration
    Patent number: 9430421
    Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: August 30, 2016
    Assignee: ARM Limited
    Inventors: Simon John Craske, Michael Alexander Kennedy, Andrew John Turner, Richard Anthony Lane
  • INTERRUPT SIGNAL ARBITRATION
    Publication number: 20150261700
    Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Inventors: Simon John Craske, Michael Alexander Kennedy, Andrew John Turner, Richard Anthony Lane
  • SPECULATIVE INTERRUPT SIGNALLING
    Publication number: 20150220465
    Abstract: A data processing system 2 includes an interrupt controller having a priority level arbitrator 10 and trigger circuitry 12. The priority level arbitrator 10 and the trigger circuitry 12 operate in parallel to process interrupt signals received by an interrupt signal receiver 6. The trigger circuitry 12 generates a trigger signal initiating interrupt processing before the priority level arbitrator 10 has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.
    Type: Application
    Filed: December 23, 2014
    Publication date: August 6, 2015
    Inventors: Michael KENNEDY, Simon John CRASKE, Andrew TURNER, Richard Anthony LANE